Usb Pll Lock Status (Upllsts) Register; Bit Clock Source Selection For Can0 (Can0Bclksel) Register; Bit Clock Source Selection For Can1 (Can1Bclksel) Register; Usb Pll Lock Status (Upllsts) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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System Control Registers

1.13.7.8 USB PLL Lock Status (UPLLSTS) Register

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 1-114. USB PLL Lock Status (UPLLSTS) Register Field Descriptions

Figure 1-104. Bit Clock Source Selection for CAN0 (CAN0BCLKSEL) Register

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 1-115. Bit Clock Source Selection for CAN0 (CAN0BCLKSEL) Register Field Descriptions

Figure 1-105. Bit Clock Source Selection for CAN1 (CAN1BCLKSEL) Register

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

System Control and Interrupts

Figure 1-103. USB PLL Lock Status (UPLLSTS) Register

USB PLL Out-of-Range Status

This bit indicates whether the PLL is out of lock range.

Note: If PLL out-of-lock condition is detected then an interrupt is generated to the NVIC; software

can decide to relock the PLL or switch to PLL bypass mode in the interrupt handler.

USB PLL is not out of lock

USB PLL is out of lock

USB PLL Lock Status

This bit indicates whether the PLL is locked or not.

USB PLL is not locked

USB PLL is locked

Bit Clock Source Select

CAN0 bit clock = M3 SS_CLK

CAN0 bit clock = OSCCLK

CAN0 bit clock = GPIO_XCLKIN

SPRUHE8E – October 2012 – Revised November 2019

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