Flash And Otp Performance; Flash Read Interface - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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FMC and C28x-FMC) which owns the pump. The pump will become active if an access is made either to
the M3-bank or the C28x-bank. Note that the PUMPRDY bit in the M3-FMC register space can be used by
the application software to identify the current power mode status of the pump and that PUMPRDY bit
(and also PMPPWR bit) in C28x-FMC cannot be used for that purpose. See register descriptions for
detailed information.

5.3.7 Flash and OTP Performance

Once flash bank and pump are in the active power state, then a read or fetch access to the bank memory
map area can be classified as a flash access (access to an address location in flash) or an OTP access
(access to an address location in OTP). Once the CPU throws an access to a flash memory address, data
is returned after RWAIT+1 number of core-specific SYSCLK cycles. For an OTP access, data is returned
after RWAIT+2 number of core-specific SYSCLK cycles.
RWAIT defines the number of random access wait states and is configurable using the RWAIT bit-field in
the FRDCNTL register. At reset, the RWAIT bit-field value defaults to a worst-case wait state count (15)
and thus, needs to be initialized for the appropriate number of wait states to improve performance, based
on the CPU clock rate and the access time of the flash.
The flash supports 0-wait accesses when the RWAIT bits are set to zero. This assumes that the CPU
speed is low enough to accommodate the access time.
For a given system clock frequency, RWAIT must be configured using the below formula:
RWAIT =[(SYSCLK/FCLK)-1] round up to the next highest integer or 1, whichever is larger
where
SYSCLK is the system operating frequency
FCLK is flash clock frequency. FCLK should be ≤ FCLKmax, allowed maximum flash clock frequency with
RWAIT=0.
If RWAIT results in a fractional value when calculated using the above formula, RWAIT has to be rounded
up to the nearest integer.

5.3.8 Flash Read Interface

This section provides details about the data read modes to access flash bank/OTP and the configuration
registers which control the read interface. In addition to a standard read mode, FMCs have built-in
prefetch and cache mechanisms to allow increased clock speeds and CPU throughput wherever
applicable.
5.3.8.1 M3-FMC Flash Read Interface
5.3.8.1.1 Standard Read Mode
Standard read mode is defined as the read mode in effect when program cache/prefetch-mechanism and
data cache are disabled. It is also the default read mode after reset. During this mode, each read access
to flash is decoded by the flash wrapper to fetch the data from the addressed location and the data is
returned after the RWAIT+1 number of cycles.
The program cache/prefetch mecahnism and data cache are bypassed in standard read mode; therefore,
every access to the flash/OTP is used by the CPU immediately and every access creates a unique flash
bank access.
Standard read mode is the recommended mode for lower system frequency operation in which RWAIT
can be set to zero to provide single cycle access operation. FMC can operate at higher frequencies using
standard read mode at the expense of adding wait states. At higher system frequencies, it is
recommended to enable cache and prefetch mechanisms to improve performance. Please refer to device
specific data manual to determine maximum flash frequency allowed in standard read mode (i.e.,
maximum flash clock frequency with one wait state - FCLKmax).
SPRUHE8E – October 2012 – Revised November 2019
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Flash Controller Memory Module
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