Table of Contents
Advertisement
Introduction
•
Comparator output signals (COMPxOUT).
Output signals from the comparator module can be fed through the GPIO peripheral [GPTRIP logic] to
one or all of the 12 trip inputs [TRIPIN1 - TRIPIN12] and in conjunction with the trip zone signals can
generate digital compare events.
•
Peripheral Bus
The peripheral bus is 32-bits wide and allows both 16-bit and 32-bit writes to the ePWM register file.
Figure 7-3. ePWM Submodules and Critical Internal Signal Interconnects
Time-Base (TB)
TBPRD Shadow (24)
TBPRD Active (24)
Counter
Up/Down
(16 Bit)
TBCTR
Active (16)
16
TBPHS Active (24)
16
CMPA Active (24)
CMPA Shadow (24)
16
CMPB Active (16)
CMPB Shadow (16)
A
These events are generated by the type 2 ePWM digital compare (DC) submodule based on the levels of the TRIPIN
inputs [For Example: COMPxOUT and TZ signals].
B
This signal exists only on devices with eQEP module
Figure 7-3
also shows the key internal submodule interconnect signals. Each submodule is described in
detail in its respective section.
672
C28 Enhanced Pulse Width Modulator (ePWM) Module
8
CTR=PRD
TBCTL[PHSEN]
CTR=ZERO
CTR_Dir
8
Phase
Control
Action
Qualifier
CTR=CMPA
(AQ)
EPWMA
CTR=CMPB
EPWMB
Copyright © 2012–2019, Texas Instruments Incorporated
CTR=ZERO
Sync
In/Out
CTR=CMPB
Select
Mux
Disabled
TBCTL[SYNCOSEL]
TBCTL[SWFSYNC]
(Software Forced
Sync)
CTR=PRD
CTR=ZERO
CTR=PRD or ZERO
CTR=CMPA
CTR=CMPB
Event
CTR_Dir
Trigger
(A)
DCAEVT1.soc
Interrupt
(A)
DCBEVT1.soc
PWM
Trip
Dead
Chopper
Zone
Band
(PC)
(TZ)
(DB)
CTR=ZERO
DCAEVT1.inter
DCBEVT1.inter
DCAEVT2.inter
DCBEVT2.inter
SPRUHE8E – October 2012 – Revised November 2019
EPWMxSYNCO
EPWMxSYNCI
DCAEVT1.sync
DCBEVT1.sync
EPWMxINT
EPWMxSOCA
EPWMxSOCB
and
EPWMxSOCA
(ET)
EPWMxSOCB
EPWMxA
EPWMxB
EPWMxTZINT
TZ1
to
TZ3
EMUSTOP
CLOCKFAIL
(B)
EQEP1ERR
(A)
DCAEVT1.force
(A)
DCAEVT2.force
(A)
DCBEVT1.force
(A)
DCBEVT2.force
Submit Documentation Feedback
www.ti.com
ADC
Advertisement
Chapters
Table of Contents
