Ssicpsr Register; Ssicpsr Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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20.5.2.5 SSICPSR Register (Offset = 10h) [reset = 0h]
SSICPSR is shown in
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SSI Clock Prescale
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit Field
31-8 RESERVED
7-0 CPSDVSR
SPRUHE8E – October 2012 – Revised November 2019
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Figure 20-14 and described in
Table.
Figure 20-14. SSICPSR Register
RESERVED
R-0h
Table 20-8. SSICPSR Register Field Descriptions
Type Reset
R 0h
R/W 0h
Copyright © 2012–2019, Texas Instruments Incorporated
Table 20-8.
9
Description
Reserved
SSI Clock Prescale Divisor
This value must be an even number from 2 to 254,
depending on the frequency of SSInClk. The LSB always returns 0
on
reads.
Reset type: PER.RESET
M3 Synchronous Serial Interface (SSI)
SSI Registers
8 7 6 5 4 3 2 1
CPSDVSR
R/W-0h
0
1465