Register Descriptions; Epi Configuration Register (Epicfg), Offset 0X000; Epi Configuration Register (Epicfg) [Offset 0X000]; Epi Configuration Register (Epicfg) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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17.11 Register Descriptions

This section lists and describes the EPI registers, in numerical order by address offset.

NOTE: The MODE field determines which configuration register is accessed for offsets 0x010 and

0x014. Any write to the EPICFG register resets the register contents at offsets 0x010 and

The configuration register is used to enable the block, select a mode, and select the basic pin use (based

on the mode). Note that attempting to program an undefined MODE field clears the BLKEN bit and

disables the EPI controller.

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 17-14. EPI Configuration Register (EPICFG) Field Descriptions

0x3-0xF Reserved

SPRUHE8E – October 2012 – Revised November 2019

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Figure 17-28. EPI Configuration Register (EPICFG) [offset 0x000]

Integer Clock Divider Enable

EPIBAUD register values create formula clock divide.

EPIBAUD register values create integer clock divide.

Block Enable

The EPI controller is disabled.

The EPI controller is enabled.

General Purpose

General-Purpose mode. Control, address, and data pins are configured using the EPIGPCFG and

EPIGPCFG2 registers.

Supports SDR SDRAM. Control, address, and data pins are configured using the EPISDRAMCFG

8-Bit Host-Bus (HB8)

Host-bus 8-bit interface (also known as the MCU interface). Control, address, and data pins are

configured using the EPIHB8CFG and EPIHB8CFG2 registers.

16-Bit Host-Bus (HB16)

Host-bus 16-bit interface (standard SRAM). Control, address, and data pins are configured using

the EPIHB16CFG and EPIHB16CFG2 registers.

External Peripheral Interface (EPI)

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