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General-Purpose Input/Output (GPIO)
4.1.3.2
Data Control
The data control registers allow software to configure the operational modes of the GPIOs. The data
direction register configures the GPIO as an input or an output while the data register either captures
incoming data or drives it out to the pads.
4.1.3.2.1 Data Direction Operation
The GPIO Direction (GPIODIR) register is used to configure each individual pin as an input or output.
When the data direction bit is cleared, the GPIO is configured as an input, and the corresponding data
register bit captures and stores the value on the GPIO port. When the data direction bit is set, the GPIO is
configured as an output, and the corresponding data register bit is driven out on the GPIO port.
4.1.3.2.2 Data Register Operation
To aid in the efficiency of software, the GPIO ports allow for the modification of individual bits in the GPIO
Data (GPIODATA) register by using bits [9:2] of the address bus as a mask. In this manner, software
drivers can modify individual GPIO pins in a single instruction without affecting the state of the other pins.
This method is more efficient than the conventional method of performing a read-modify-write operation to
set or clear an individual GPIO pin. To implement this feature, the GPIODATA register covers 256
locations in the memory map.
During a write, if the address bit associated with that data bit is set, the value of the GPIODATA register is
altered. If the address bit is cleared, the data bit is left unchanged.
For example, writing a value of 0xEB to the address GPIODATA + 0x098 has the results shown in , where
u indicates that data is unchanged by the write.
During a read, if the address bit associated with the data bit is set, the value is read. If the address bit
associated with the data bit is cleared, the data bit is read as a zero, regardless of its actual value. For
example, reading address GPIODATA + 0x0C4 yields as shown in .
352
General-Purpose Input/Output (GPIO)
Figure 4-2. GPIODATA Write Example
ADDR[9:2]
9
8
7
6
5
0x098
0
0
1
0
0
0xEB
1
1
1
0
1
GPIODATA
u
u
1
u
u
7
6
5
4
3
Figure 4-3. GPIODATA Read Example
ADDR[9:2]
9
8
7
6
0x0C4
0
0
1
1
GPIODATA
1
0
1
1
Returned V alue
0
0
1
1
7
6
5
4
Copyright © 2012–2019, Texas Instruments Incorporated
4
3
2
1
0
1
1
0
0
0
0
1
1
0
1
u
2
1
0
5
4
3
2
1
0
0
0
0
1
0
0
1
1
1
0
0
0
0
0
3
2
1
0
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
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