Channel Control Word Configuration For Peripheral Ping-Pong Receive Example - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Table 16-11. Primary and Alternate Channel Control Structure Offsets for Channel 8 (continued)
Control Table Base + 0x088
Control Table Base + 0x280
Control Table Base + 0x284
Control Table Base + 0x288
16.4.4.2.1 Configure the Source and Destination
The source and destination end pointers must be set to the last address for the transfer (inclusive).
Because the peripheral pointer does not change, it simply points to the peripheral's data register. Both the
primary and alternate sets of pointers must be configured.
• Program the primary source end pointer at offset 0x080 to the address of the peripheral's receive
buffer.
• Program the primary destination end pointer at offset 0x084 to the address of ping-pong buffer A +
0x3F.
• Program the alternate source end pointer at offset 0x280 to the address of the peripheral's receive
buffer.
• Program the alternate destination end pointer at offset 0x284 to the address of ping-pong buffer B +
0x3F.
The primary control word at offset 0x088 and the alternate control word at offset 0x288 are initially
programmed the same way.
• Program the primary channel control word at offset 0x088 according to
• Program the alternate channel control word at offset 0x288 according to
Table 16-12. Channel Control Word Configuration for Peripheral Ping-Pong Receive Example
Field in DMACHCTL
DSTINC
DSTSIZE
SRCINC
SRCSIZE
reserved
ARBSIZE
XFERSIZE
NXTUSEBURST
XFERMODE
NOTE: In this example, it is not important if the peripheral makes a single request or a burst request.
Because the peripheral has a FIFO that triggers at a level of 8, the arbitration size is set to 8.
If the peripheral does make a burst request, then 8 bytes are transferred, which is what the
FIFO can accommodate. If the peripheral makes a single request (if there is any data in the
FIFO), then one byte is transferred at a time. If it is important to the application that transfers
only be made in bursts, then the Channel Useburst SET[8] bit should be set in the DMA
Channel Useburst Set (DMAUSEBURSTSET) register.
SPRUHE8E – October 2012 – Revised November 2019
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Offset
Bits
31:30
29:28
27:26
25:24
23:18
17:14
13:4
3
2:0
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Initialization and Configuration
Description
Channel 8 Primary Control Word
Channel 8 Alternate Source End Pointer
Channel 8 Alternate Destination End Pointer
Channel 8 Alternate Control Word
Table 16-12.
Table 16-12.
Value
8-bit destination address
0
0 8-bit destination data size
Source address does not
3
0 8-bit source data size
0
3 Arbitrates after 8 transfers
63 Transfer 64 items
0 N/A for this transfer type
3 Use Ping-Pong transfer mode
M3 Micro Direct Memory Access ( µDMA)
Description
increment
increment
Reserved
1205