Usb Control And Status Endpoint 0 High Register (Usbcsrh0), Offset 0X103; Usb Control And Status Endpoint 0 High Register (Usbcsrh0) In Otg A/Host Mode; Usb Control And Status Endpoint 0 High Register (Usbcsrh0) In Otg B/Device Mode; Usb Control And Status Endpoint 0 High Register (Usbcsrh0) In Otg A/Host Mode Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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18.5.30 USB Control and Status Endpoint 0 High Register (USBCSRH0), offset 0x103

The USB control and status endpoint 0 high 8-bit register (USBCSRH0) provides control and status bits
for endpoint 0.
Mode(s): OTG A or Host
USBCSRH0 in OTG A/Host mode is shown in
Figure 18-36. USB Control and Status Endpoint 0 High Register (USBCSRH0) in OTG A/Host Mode
7
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18-39. USB Control and Status Endpoint 0 High Register (USBCSRH0) in OTG A/Host Mode
Bit Field Value
7-3 Reserved 0
2 DTWE
0
1
1 DT
0 FLUSH
0
1
USBCSRH0 in OTG B/Device mode is shown in
Figure 18-37. USB Control and Status Endpoint 0 High Register (USBCSRH0) in OTG B/Device
7
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18-40. USB Control and Status Endpoint 0 High Register (USBCSRH0) in OTG B/Device Mode
Bit Field Value
7-1 Reserved 0
0 FLUSH
0
1
SPRUHE8E – October 2012 – Revised November 2019
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OTG B or Device
Figure 18-36
Reserved
R-0
Field Descriptions
Description
Reserved
Data Toggle Write Enable. This bit is automatically cleared once the new value is written.
The DT bit cannot be written.
Enables the current state of the endpoint 0 data toggle to be written (see DT bit).
Data Toggle. When read, this bit indicates the current state of the endpoint 0 data toggle.
If DTWE is set, this bit may be written with the required setting of the data toggle. If DTWE is Low, this
bit cannot be written. Care should be taken when writing to this bit as it should only be changed to
RESET USB endpoint 0.
Flush FIFO. This bit is automatically cleared after the flush is performed.
No effect
Flushes the next packet to be transmitted/read from the endpoint 0 FIFO. The FIFO pointer is reset and
the TXRDY/RXRDY bit is cleared.
Note: This bit should only be set when TXRDY/RXRDY is set. At other times, it may cause data to be
corrupted.
Reserved
R-0
Field Descriptions
Description
Reserved
Flush FIFO. This bit is automatically cleared after the flush is performed.
No effect
Flushes the next packet to be transmitted/read from the endpoint 0 FIFO. The FIFO pointer is reset and
the TXRDY/RXRDY bit is cleared.
Note: This bit should only be set when TXRDY/RXRDY is set. At other times, it may cause data to be
corrupted.
Copyright © 2012–2019, Texas Instruments Incorporated
and described in
3 2
DTWE
R/W-0
Figure 18-37 and described in
Mode
M3 Universal Serial Bus (USB) Controller
Register Descriptions
Table 18-39.
1 0
DT FLUSH
R/W-0 R/W-0
Table 18-40.
1 0
FLUSH
R/W-0
1373