Hard Fault Status (Hfaultstat) Register; Hard Fault Status (Hfaultstat) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

System Control Block (SCB) Register Descriptions
25.6.13 Hard Fault Status (HFAULTSTAT) Register, offset 0xD2C
The Hard Fault Status (HFAULTSTAT) register gives information about events that activate the hard fault
handler. Bits are cleared by writing a 1 to them.
Note: This register can only be accessed from privileged mode.
31 30
DBG FORCED
R/W-1C R/W-1C
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-51. Hard Fault Status (HFAULTSTAT) Register Field Descriptions
Bit Field
31 DBG
30 FORCED
29-2 Reserved
1 VECT
0 Reserved
1684
Cortex-M3 Peripherals
Figure 25-44. Hard Fault Status (HFAULTSTAT) Register
29
Reserved
R-0
Value Description
Debug Event
This bit is reserved for Debug use. This bit must be written as a 0, otherwise behavior is
unpredictable.
Forced Hard Fault
0 No forced hard fault has occurred.
1 A forced hard fault has been generated by escalation of a fault with configurable priority that cannot
be handled, either because of priority or because it is disabled.
When this bit is set, the hard fault handler must read the other fault status registers to find the
cause of the fault.
This bit is cleared by writing a 1 to it.
Reserved
Vector Table Read Fault
0 No bus fault has occurred on a vector table read.
1 A bus fault occurred on a vector table read.
This error is always handled by the hard fault handler. When this bit is set, the PC value stacked for
the exception return points to the instruction that was preempted by the exception.
This bit is cleared by writing a 1 to it.
Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
2 1
VECT
SPRUHE8E – October 2012 – Revised November 2019
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16
0
Reserved
R-0