Table Of Contents - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Preface
1 System Control and Interrupts
1.1 Signal Description
1.2 System Control Functional Description
1.2.1 Device Identification
1.2.2 Device Configuration Registers
1.3 Reset Control
1.3.1 Device Level Reset Sources
1.3.2 Handling of Resets at System Level
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1.4 WIR Mode
1.4.1 Entering WIR Mode
1.4.2 Exiting WIR Mode
1.5 Exceptions and Interrupts Control
1.5.1 Master Subsystem Nested Vectored Interrupt Controller
1.5.2 Master Subsystem Exceptions Handling
1.5.3 Master Subsystem Non-Maskable Interrupt (MNMI) Module
1.5.4 Control Subsystem PIE
1.5.5 Control Subsystem Exceptions Handling
1.5.6 Control Subsystem NMI (CNMI) Module
1.6 Safety Features
1.6.1 Write Protection on Registers
1.6.2 Missing Clock Detection Logic
1.6.3 PLLSLIP Detection
1.6.4 Control Subsystem PIE Vector Address Validity Check
1.6.5 NMIWDs
1.6.6 Watchdog Timers
1.6.7 ECC and Parity Enabled RAMs, Shared RAMs Protection
1.6.8 ECC Enabled Flash Memory
1.7 Power Control
1.8 Clock Control
1.8.1 Clock Sources
1.8.2 PLLs
1.8.3 Master Subsystem Clocking
1.8.4 Control Subsystem Clocking
1.8.5 Clocking Control Semaphore Functionality
1.8.6 ACIB and Analog Peripherals Clocking
1.8.7 Configuring XCLKOUT
1.8.8 32-Bit CPU Timers 0/1/2
1.9 Low Power Modes
1.9.1 Low-Power Modes
1.10 Code Security Module (CSM)
1.10.1 Functional Description
1.10.2 CSM Impact on Other On-Chip Resources
1.10.3 Incorporating Code Security in User Applications
1.10.4 Do's and Don'ts to Protect Security Logic
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Copyright © 2012-2019, Texas Instruments Incorporated
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SPRUHE8E - October 2012 - Revised November 2019
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