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The M3 GPIO Mux also contains an alternate muxing mode. The proper bits in the Alternate Peripheral
Select (GPIOAPSEL) register must be set to access these muxing options. The Digital Function
(GPIOPCTL) register can then be used to select the mux option.
4.1.3 Functional Description
Each GPIO port is a separate hardware instantiation of the same physical block (see
microcontroller contains nine ports and therefore nine of these physical GPIO blocks. Note that not all pins
may be implemented on every block. Some GPIO pins can function as I/O signals for the on-chip
peripheral modules.
Port
Commit
Control
Control
GPIOPCTL
GPIOLOCK
GPIOAPSEL
GPIOCR
Periph 0
Periph 1
Alternate OutputEnable
Periph n
Data
Control
GPIODATA
GPIODIR
Interrupt
Control
GPIOIS
Interrupt
GPIOIBE
GPIOIEV
GPIOIM
GPIORIS
GPIOMIS
GPIOICR
GPIOPeriphID0
GPIOPeriphID1
GPIOPeriphID2
GPIOPeriphID3
4.1.3.1
Master Control
The M3 GPIO mux is the master, and at boot time, the user needs to allocate which core (M3 or C28)
controls which pin. By default, all pins are assigned to the M3 GPIO mux except Group 2 GPIOs. See
Section 4.2
for more information.
To select which core controls a GPIO pin, use the GPIO Core Select (GPIOCSEL) register. If the M3
GPIOs are enabled by the GPIODEN register, the M3 can still monitor any GPIO, even if it is mapped to
the C28 GPIO mux.
SPRUHE8E – October 2012 – Revised November 2019
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Figure 4-1. Digital I/O Pads
Mode
Control
GPIOAFSEL
Alternate Input
Alternate Output
GPIO Input
GPIO Output
GPIO OutputEnable
Pad
Control
GPIOPUR
GPIOODR
GPIODEN
GPIOAMSEL
GPIOCSEL
Identification Registers
GPIOPeriphID4
GPIOPCellID0
GPIOPeriphID5
GPIOPCellID1
GPIOPeriphID6
GPIOPCellID2
GPIOPeriphID7
GPIOPCellID3
Copyright © 2012–2019, Texas Instruments Incorporated
General-Purpose Input/Output (GPIO)
Pad Input
Digital
Pad Output
I/O
Pad
Pad Output
Enable
General-Purpose Input/Output (GPIO)
Figure
4-1). The
Package I/OPin
351
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