Comparator Block
Table 10-37. COMPCTL Register Field Descriptions (continued)
Bit
Field
7-3
QUALSEL
2
CMPINV
1
COMPSOURCE
0
COMPDACEN
10.4.7.2 Compare Output Status (COMPSTS) Register
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-38. Compare Output Status (COMPSTS) Register Field Descriptions
Bit
Field
15-1
Reserved
0
COMPSTS
10.4.7.3 DAC Value (DACVAL) Register
15
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
Field
15-10
Reserved
9-0
DACVAL
942
Analog Subsystem
Value
Description
Qualification Period for synchronized output of the comparator
0h
Synchronized value of comparator is passed through
1h
Input to the block must be consistent for 2 consecutive clocks before output of Qual block can
change
2h
Input to the block must be consistent for 3 consecutive clocks before output of Qual block can
change
...
...
Fh
Input to the block must be consistent for 16 consecutive clocks before output of Qual block can
change
Invert select for Comparator
0
Output of comparator is passed
1
Inverted output of comparator is passed
Source select for comparator inverting input
0
Inverting input of comparator connected to internal DAC
1
Inverting input connected to external pin
Comparator/DAC Enable
0
Comparator/DAC logic is powered down.
1
Comparator/DAC logic is powered up.
Figure 10-56. Compare Output Status (COMPSTS) Register
Reserved
R-0
Value
Description
Reserved
Logical latched value of the comparator
Figure 10-57. DAC Value (DACVAL) Register
10
9
Table 10-39. DAC Value (DACVAL) Register Field Descriptions
Value
Description
Reserved
0-3FFh DAC Value bits, scales the output of the DAC from 0 – 1023.
Copyright © 2012–2019, Texas Instruments Incorporated
DACVAL
R/W-0
SPRUHE8E – October 2012 – Revised November 2019
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1
0
COMPSTS
R-0
0