Gptm Interrupt Clear (Gptmicr) Register, Offset 0X024; Gptm Masked Interrupt Status (Gptmmis) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Table 2-11. GPTM Masked Interrupt Status (GPTMMIS) Register Field Descriptions
Bit Field
31-12
11 TBMMIS
10 CBEMIS
9 CBMMIS
8 TBTOMIS
7-5 Reserved
4 TAMMIS
3 RTCMIS
2 CAEMIS
1 CAMMIS
0 TATOMIS

2.6.8 GPTM Interrupt Clear (GPTMICR) Register, offset 0x024

The GPTM Interrupt Clear (GPTMICR) register is used to clear the status bits in the GPTMRIS and
GPTMMIS registers. Writing a 1 to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS
registers.
SPRUHE8E – October 2012 – Revised November 2019
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Value Description
Reserved
GPTM Timer B Mode Match Masked Interrupt
0 A Timer B Mode Match interrupt has not occurred or is masked.
1 An unmasked Timer B Mode Match interrupt has occurred.
This bit is cleared by writing a 1 to the TBMCINT bit in the GPTMICR register.
GPTM Capture B Event Masked Interrupt
0 A Capture B event interrupt has not occurred or is masked.
1 An unmasked Capture B event interrupt has occurred.
This bit is cleared by writing a 1 to the CBECINT bit in the GPTMICR register.
GPTM Capture B Match Masked Interrupt
0 A Capture B Mode Match interrupt has not occurred or is masked.
1 An unmasked Capture B Match interrupt has occurred.
This bit is cleared by writing a 1 to the CBMCINT bit in the GPTMICR register.
GPTM Timer B Time-Out Masked Interrupt
0 A Timer B Time-Out interrupt has not occurred or is masked.
1 An unmasked Timer B Time-Out interrupt has occurred.
This bit is cleared by writing a 1 to the TBTOCINT bit in the GPTMICR register.
GPTM Timer A Mode Match Raw Interrupt
0 A Timer A Mode Match interrupt has not occurred or is masked.
1 An unmasked Timer A Mode Match interrupt has occurred.
This bit is cleared by writing a 1 to the TAMCINT bit in the GPTMICR register
GPTM RTC Masked Interrupt
0 The RTC event has not occurred.
1 The RTC event has occurred.
This bit is cleared by writing a 1 to the RTCCINT bit in the GPTMICR register.
GPTM Capture A Event Masked Interrupt
0 A Capture A event interrupt has not occurred or is masked.
1 An unmasked Capture A event interrupt has occurred.
This bit is cleared by writing a 1 to the CAECINT bit in the GPTMICR register.
GPTM Capture A Match Masked Interrupt
0 A Capture A Mode Match interrupt has not occurred or is masked.
1 An unmasked Capture A Match interrupt has occurred.
This bit is cleared by writing a 1 to the CAMCINT bit in the GPTMICR register.
GPTM Timer A Time-Out Masked Interrupt
0 A Timer A Time-Out interrupt has not occurred or is masked.
1 An unmasked Timer A Time-Out interrupt has occurred..
This bit is cleared by writing a 1 to the TATOCINT bit in the GPTMICR register.
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Register Descriptions
M3 General-Purpose Timers
323