Possible Inputs To The Sample Rate Generator And The Polarity Bits; Polarity Options For The Input To The Sample Rate Generator - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Figure 15-18. Possible Inputs to the Sample Rate Generator and the Polarity Bits
MCLKX pin
MCLKR pin
Table 15-6. Polarity Options for the Input to the Sample Rate Generator
Input Clock
LSPCLK
Signal on MCLKR pin
Signal on MCLKX pin
15.4.1.4 Choosing a Frequency for the Output Clock (CLKG)
The input clock (LSPCLK or external clock) can be divided down by a programmable value to drive CLKG.
Regardless of the source to the sample rate generator, the rising edge of CLKSRG (see
generates CLKG and FSG.
The first divider stage of the sample rate generator creates the output clock from the input clock. This
divider stage uses a counter that is preloaded with the divide down value in the CLKGDV bits of SRGR1.
The output of this stage is the data clock (CLKG). CLKG has the frequency represented by Example 3.
Equation 3: CLKG Frequency
Thus, the input clock frequency is divided by a value between 1 and 256. When CLKGDV is odd or equal
to 0, the CLKG duty cycle is 50%. When CLKGDV is an even value, 2p, representing an odd divide down,
the high-state duration is p+1 cycles and the low-state duration is p cycles.
15.4.1.5 Keeping CLKG Synchronized to External MCLKR
When the MCLKR pin is used to drive the sample rate generator (see
SRGR2 and the FSR pin can be used to configure the timing of the output clock (CLKG) relative to the
input clock. Note that this feature is available only when the MCLKR pin is used to feed the external clock.
GSYNC = 1 ensures that the McBSP and an external device are dividing down the input clock with the
same phase relationship. If GSYNC = 1, an inactive-to-active transition on the FSR pin triggers a
resynchronization of CLKG and generation of FSG.
For more details about synchronization, see
SPRUHE8E – October 2012 – Revised November 2019
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CLKXP
CLKRP
CLKSM
LSPCLK
Reserved
Polarity Option
Always positive polarity
CLKRP = 0 in PCR
CLKRP = 1 in PCR
CLKXP = 0 in PCR
CLKXP = 1 in PCR
CLKG frequency +
Copyright © 2012–2019, Texas Instruments Incorporated
1
0
1
CLKSRG
0
1
SCLKME
0
Effect
Rising edge of CPU clock generates transitions on CLKG and FSG.
Falling edge on MCLKR pin generates transitions on CLKG and FSG.
Rising edge on MCLKR pin generates transitions on CLKG and FSG.
Rising edge on MCLKX pin generates transitions on CLKG and FSG.
Falling edge on MCLKX pin generates transitions on CLKG and FSG.
Input clock frequency
( CLKGDV ) 1 )
Section 15.4.3.
C28 Multichannel Buffered Serial Port (McBSP)
McBSP Sample Rate Generator
To clock dividers
Figure
Section 15.4.1.2), the GSYNC bit in
15-17)
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