Serial Port Control Registers (Spcr[1,2]); Serial Port Control 1 Register (Spcr1); Serial Port Control 1 Register (Spcr1) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

McBSP Registers

15.12.4 Serial Port Control Registers (SPCR[1,2])

Each McBSP has two serial port control registers, SPCR1
registers enable you to:
• Control various McBSP modes: digital loopback mode (DLB), sign-extension and justification mode for
reception (RJUST), clock stop mode (CLKSTP), interrupt modes (RINTM and XINTM), emulation mode
(FREE and SOFT)
• Turn on and off the DX-pin delay enabler (DXENA)
• Check the status of receive and transmit operations (RSYNCERR, XSYNCERR, RFULL, XEMPTY,
RRDY, XRDY)
• Reset portions of the McBSP (RRST, XRST, FRST, GRST)

15.12.4.1 Serial Port Control 1 Register (SPCR1)

The serial port control 1 register (SPCR1) is shown in
15 14
DLB
R/W-0
7 6
DXENA Reserved
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15-72. Serial Port Control 1 Register (SPCR1) Field Descriptions
Bit Field
15 DLB
14-13 RJUST
1158
C28 Multichannel Buffered Serial Port (McBSP)
Figure 15-67. Serial Port Control 1 Register (SPCR1)
13 12
RJUST
R/W-0
5 4
RINTM
R/W-0
Value Description
Digital loopback mode bit. DLB disables or enables the digital loopback mode of the McBSP:
0 Disabled
Internal DR is supplied by the MDRx pin. Internal FSR and internal MCLKR can be supplied by their
respective pins or by the sample rate generator, depending on the mode bits FSRM and CLKRM.
Internal DX is supplied by the MDXx pin. Internal FSX and internal CLKX are supplied by their
respective pins or are generated internally, depending on the mode bits FSXM and CLKXM.
1 Enabled
Internal receive signals are supplied by internal transmit signals:
MDRx connected to MDXx
MFSRx connected to MFSXx
MCLKR connected to MCLKXx
This mode allows you to test serial port code with a single DSP. The McBSP transmitter directly
supplies data, frame synchronization, and clocking to the McBSP receiver.
0-3h Receive sign-extension and justification mode bits. During reception, RJUST determines how data
is justified and bit filled before being passed to the data receive registers (DRR1, DRR2).
RJUST is ignored if you enable a companding mode with the RCOMPAND bits. In a companding
mode, the 8-bit compressed data in RBR1 is expanded to left-justified 16-bit data in DRR1.
For more details about the effects of RJUST, see
and Justification Mode
0 Right justify the data and zero fill the MSBs.
1h Right justify the data and sign-extend the data into the MSBs.
2h Left justify the data and zero fill the LSBs.
3h Reserved (do not use)
Copyright © 2012–2019, Texas Instruments Incorporated
(Table 15-72) and SPCR2
Figure 15-67 and described in
11 10
CLKSTP
R/W-0
3 2
RSYNCERR RFULL
R/W-0 R-0
Section
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
(Table 15-73). These
Table 15-72.
Reserved
R-0
1
RRDY RRST
R-0 R/W-0
15.8.13, Set the Receive Sign-Extension
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