Spi Baud Rate Register (Spibrr) - Address 7044H; Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

SPI Registers and Waveforms
Table 12-11. SPI Status Register (SPIST) Field Descriptions (continued)
Bit Field
6 SPI INT FLAG
5 TX BUF FULL
FLAG
4-0 Reserved
12.3.1.4 SPI Baud Rate Register (SPIBRR)
SPIBRR contains the bits used for baud-rate selection.
7 6
Reserved SPI BIT RATE 6
R-0 RW-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
7 Reserved
6-0 SPI BIT RATE 6−
SPI BIT RATE 0
12.3.1.5 SPI Emulation Buffer Register (SPIRXEMU)
SPIRXEMU contains the received data. Reading SPIRXEMU does not clear the SPI INT FLAG bit
(SPISTS.6). This is not a real register but a dummy address from which the contents of SPIRXBUF can be
read by the emulator without clearing the SPI INT FLAG.
1004
C28 Serial Peripheral Interface (SPI)
Value Description
SPI Interrupt Flag. SPI INT FLAG is a read-only flag. The SPI hardware sets this bit to indicate that
it has completed sending or receiving the last bit and is ready to be serviced. The received
character is placed in the receiver buffer at the same time this bit is set. This flag causes an
interrupt to be requested if the SPI INT ENA bit (SPICTL.0) is set.
0 Writing a 0 has no effect
1 This bit is cleared in one of three ways:
• Reading SPIRXBUF
• Writing a 0 to SPI SW RESET (SPICCR.7)
• Resetting the system
SPI Transmit Buffer Full Flag. This read-only bit gets set to 1 when a character is written to the SPI
Transmit buffer SPITXBUF. It is cleared when the character is automatically loaded into SPIDAT
when the shifting out of a previous character is complete.
0 Writing a 0 has no effect
1 This bit is cleared at reset.
0 Reads return zero; writes have no effect.
Figure 12-16. SPI Baud Rate Register (SPIBRR) — Address 7044h
5 4
SPI BIT RATE 5 SPI BIT RATE 4
RW-0 RW-0
Table 12-12. Field Descriptions
Value Description
Reads return zero; writes have no effect.
SPI Bit Rate (Baud) Control. These bits determine the bit transfer rate if the SPI is the network
master. There are 125 data-transfer rates (each a function of the CPU clock, LSPCLK) that can be
selected. One data bit is shifted per SPICLK cycle. (SPICLK is the baud rate clock output on the
SPICLK pin.)
If the SPI is a network slave, the module receives a clock on the SPICLK pin from the network
master; therefore, these bits have no effect on the SPICLK signal. The frequency of the input clock
from the master should not exceed the slave SPI's LSPCLK signal divided by 4.
In master mode, the SPI clock is generated by the SPI and is output on the SPICLK pin. The SPI
baud rates are determined by the following formula:
For SPIBRR = 3 to 127:
For SPIBRR = 0, 1, or 2:
where: LSPCLK = Function of CPU clock frequency X low-speed peripheral clock of the device
SPIBRR = Contents of the SPIBRR in the master SPI device
Copyright © 2012–2019, Texas Instruments Incorporated
3 2
SPI BIT RATE 3 SPI BIT RATE 2
RW-0 RW-0
LSPCLK
=
SPI Baud Rate
+
(SPIBRR 1)
LSPCLK
SPI Baud Rate =
4
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
1 0
SPI BIT RATE 1 SPI BIT RATE 0
RW-0 RW-0
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