I2C Mode Register (I2Cmdr); I2C Mode Register (I2Cmdr) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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14.5.1 I2C Mode Register (I2CMDR)

The I2C mode register (I2CMDR) is a 16-bit register that contains the control bits of the I2C module. The
bit fields of I2CMDR are shown in
15 14
NACKMOD FREE
R/W-0 R/W-0
7 6
RM DLB
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
15 NACKMOD
14 FREE
13 STT
12 Reserved
11 STP
SPRUHE8E – October 2012 – Revised November 2019
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Figure 14-14
Figure 14-14. I2C Mode Register (I2CMDR)
13 12
STT Reserved
R/W-0 R/W-0
5 4
IRS STB
R/W-0 R/W-0
Table 14-5. I2C Mode Register (I2CMDR) Field Descriptions
Value Description
NACK mode bit. This bit is only applicable when the I2C module is acting as a receiver.
0 In the slave-receiver mode: The I2C module sends an acknowledge (ACK) bit to the transmitter
during each acknowledge cycle on the bus. The I2C module only sends a no-acknowledge (NACK)
bit if you set the NACKMOD bit.
In the master-receiver mode: The I2C module sends an ACK bit during each acknowledge cycle
until the internal data counter counts down to 0. At that point, the I2C module sends a NACK bit to
the transmitter. To have a NACK bit sent earlier, you must set the NACKMOD bit.
1 In either slave-receiver or master-receiver mode: The I2C module sends a NACK bit to the
transmitter during the next acknowledge cycle on the bus. Once the NACK bit has been sent,
NACKMOD is cleared.
Important: To send a NACK bit in the next acknowledge cycle, you must set NACKMOD before the
rising edge of the last data bit.
This bit controls the action taken by the I2C module when a debugger breakpoint is encountered.
0 When I2C module is master:
If SCL is low when the breakpoint occurs, the I2C module stops immediately and keeps driving SCL
low, whether the I2C module is the transmitter or the receiver. If SCL is high, the I2C module waits
until SCL becomes low and then stops.
When I2C module is slave:
A breakpoint forces the I2C module to stop when the current transmission/reception is complete.
1 The I2C module runs free; that is, it continues to operate when a breakpoint occurs.
START condition bit (only applicable when the I2C module is a master). The RM, STT, and STP
bits determine when the I2C module starts and stops data transmissions (see
that the STT and STP bits can be used to terminate the repeat mode, and that this bit is not
writable when IRS = 0.
0 In the master mode, STT is automatically cleared after the START condition has been generated.
1 In the master mode, setting STT to 1 causes the I2C module to generate a START condition on the
I2C-bus.
This reserved bit location is always read as a 0. A value written to this bit has no effect.
STOP condition bit (only applicable when the I2C module is a master). In the master mode, the RM,
STT, and STP bits determine when the I2C module starts and stops data transmissions (see
Table 14-6). Note that the STT and STP bits can be used to terminate the repeat mode, and that
this bit is not writable when IRS=0. When in non-repeat mode, at least one byte must be transferred
before a stop condition can be generated. The I2C module delays clearing of this bit until ater the
I2CSTR[SCD] bit is set. If the STOP bit is not checked prior to initiating a new message, the I2C
module could become confused. To avoid disrupting the I2C state machine, the user must wait until
this bit is clear before initiating a new message.
0 STP is automatically cleared after the STOP condition has been generated.
1 STP has been set by the device to generate a STOP condition when the internal data counter of
the I2C module counts down to 0.
Copyright © 2012–2019, Texas Instruments Incorporated
and described in Table 14-5.
11 10
STP MST
R/W-0 R/W-0
3 2
FDF
R/W-0
C28 Inter-Integrated Circuit Module
I2C Module Registers
9 8
TRX XA
R/W-0 R/W-0
0
BC
R/W-0
Table 14-6). Note
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