Write Cycle; Sdram Normal Read Cycle - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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CLK
(EPI0S31)
CKE
(EPI0S30)
CS
(EPI0S29)
WE
(EPI0S28)
RAS
(EPI0S19)
CAS
(EPI0S18)
DQMH, DQML
(EPI0S [17:16])
AD [15:0]
Row
(EPI0S [15:0])
Activate
AD [15:0]drivenout

17.6.6 Write Cycle

Figure 17-4 shows a write cycle of n halfwords; n can be any number greater than or equal to 1. The cycle
begins with the Activate command and the row address on the EPI0S[15:0] signals. With the programmed
CAS latency of 2, the Write command with the column address on the EPI0S[15:0] signals follows after
two clock cycles. When writing to SDRAMs, the Write command is presented with the first halfword of
data. Because the address lines and the data lines are multiplexed, the column address is modified to be
(programmed address -1). During the Write command, the DQMH and DQML signals are high, so no data
is written to the SDRAM. On the next clock, the DQMH and DQML signals are asserted, and the data
associated with the programmed address is written. The Burst Terminate command occurs during the
clock cycle following the write of the last halfword of data. The WE, DQMH, DQML, and CS signals are
deasserted after the last halfword of data is received, signaling the end of the access. At least one clock
period of inactivity separates any two SDRAM cycles.
SPRUHE8E – October 2012 – Revised November 2019
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Figure 17-3. SDRAM Normal Read Cycle
Column-1
NOP NOP Write
Copyright © 2012–2019, Texas Instruments Incorporated
Data 0 Data 1 ...
AD [15:0]drivenout
External Peripheral Interface (EPI)
SDRAM Mode
Data n
Burst
Term
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