Deep Sleep Clock Configuration (Dslpclkcfg) Register; Deep Sleep Clock Configuration (Dslpclkcfg) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

System Control Registers
Figure 1-123. Deep Sleep Clock Configuration (DSLPCLKCFG) Register
31
Reserved
R-0:0
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-134. Deep Sleep Clock Configuration (DSLPCLKCFG) Register Field Descriptions
Bit Field
31-27 Reserved
26-23 DSDIVOVRIDE
22-7 Reserved
6-4 DSOSCSRC
3-0 Reserved
248
System Control and Interrupts
27 26
DSDIVOVRIDE
R/W-0
Reserved
R-0
Value Description
Reserved
Deep Sleep Divider Override
Divider field override in deep sleep mode.
If Deep Sleep mode is enabled when the PLL is running, the PLL is disabled. This 6-bit field
contains a system divider field that overrides the M3SSDIVSEL register. This divider is applied
to the source selected by the DSOSCSRC field.
0x0 /1
0x1 /2
0x2 /3
0x3 /4
0x4 /5
0x5 /6
0x6 /7
0x7 /8
0x8 /9
0x9 /10
0xA /11
0xB /12
0xC /13
0xD /14
0xE /15
0xF /16
Reserved
Deep Sleep Mode Clock Source Select
0x0 Use OSCCLK as the clock source
0x1 Use the 32-kHz clock as the clock source
0x2 Use the 10-MHz ATOB clock as the clock source
0x3-0x7 Reserved
Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
23 22
7 6 4
DSOSCSRC
R/W-0:0
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
16
Reserved
R-0
3 0
Reserved
R-0
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