Timerxprd Register (X = 0, 1, 2); Timerxprdh Register (X = 0, 1, 2); Timerxtcr Register (X = 0, 1, 2); Timerxtimh Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

SPRUHE8E – October 2012 – Revised November 2019

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Table 1-18. TIMERxTIMH Register Field Descriptions

See description for TIMERxTIM.

Figure 1-18. TIMERxPRD Register (x = 0, 1, 2)

Table 1-19. TIMERxPRD Register Field Descriptions

CPU-Timer Period Registers (PRDH:PRD): The PRD register holds the low 16 bits of the 32-bit period. The

PRDH register holds the high 16 bits of the 32-bit period. When the TIMH:TIM decrements to zero, the

TIMH:TIM register is reloaded with the period value contained in the PRDH:PRD registers, at the start of

the next timer input clock cycle (the output of the prescaler). The PRDH:PRD contents are also loaded into

the TIMH:TIM when you set the timer reload bit (TRB) in the Timer Control Register (TCR).

Figure 1-19. TIMERxPRDH Register (x = 0, 1, 2)

Table 1-20. TIMERxPRDH Register Field Descriptions

See description for TIMERxPRD

Figure 1-20. TIMERxTCR Register (x = 0, 1, 2)

Table 1-21. TIMERxTCR Register Field Descriptions

CPU-Timer Interrupt Flag

TIF indicates whether a timer overflow has happened since TIF was last cleared. TIF is

not cleared automatically and does not need to be cleared to enable the next timer

The CPU-Timer has not decremented to zero.

Writes of 0 are ignored.

This flag gets set when the CPU-timer decrements to zero.

Writing a 1 to this bit clears the flag.

Clock Control

System Control and Interrupts

Chapters

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