Epi Read Size 0 (Epirsize0) Register And Epi Read Size 1 (Epirsize1) Register, Offset 0X020 And 0X030 - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Register Descriptions
Table 17-24. EPI Address Map (EPIADDRMAP) Register Field Descriptions (continued)
Bit Field
9-8 ECADR
7-6 EPSZ
5-4 EPADR
3-2 ERSZ
1-0 ERADR
17.11.12 EPI Read Size 0 (EPIRSIZE0) Register and EPI Read Size 1 (EPIRSIZE1) Register,
offset 0x020 and 0x030
The SIZE field must match the external data width as configured in the EPIHBnCFG or EPIGPCFG
register if the WORD bit is clear in the EPIHBnCFG2 or EPIGPCFG2 register. If the WORD bit is set, the
SIZE field must be greater than or equal to the external data width.
SDRAM mode uses a 16-bit data interface. If SIZE is 0x1, data is returned on the least significant bits
(D[7:0]), and the remaining bits D[31:8] are all zeros, therefore the data on bits D[15:8] is lost. If SIZE is
0x2, data is returned on the least significant bits (D[15:0]), and the remaining bits D[31:16] are all zeros.
Note that changing this register while a read is active has an unpredictable effect.
1286
External Peripheral Interface (EPI)
Value Description
External Code Address
This field selects address mapping for the external code area.
0x0 Not mapped
0x1 At 0x1000.0000
0x2 Reserved
0x3 Reserved
External Peripheral Size
This field selects the size of the external peripheral. If the size of the external peripheral is larger, a
bus fault occurs. If the size of the external peripheral is smaller, it wraps (upper address bits
unused).
Note: When not using byte selects in Host-Bus 16, data is accessed on 2-byte boundaries. As a
result, the available address space is double the amount shown below.
0x0 256 bytes; lower address range: 0x00 to 0xFF
0x1 64 KB; lower address range: 0x0000 to 0xFFFF
0x2 16 MB; lower address range: 0x00.0000 to 0xFF.FFFF
0x3 512 MB; lower address range: 0x000.0000 to 0x1FFF.FFFF
External Peripheral Address
This field selects address mapping for the external peripheral area.
0x0 Not mapped.
0x1 At 0xA000.0000
0x2 At 0xC000.0000
0x3 Only to be used with Host Bus quad chip select. In quad chip select mode, CS2 maps to
0xA000.0000 and CS3 maps to 0xC000.0000.
External RAM Size
This field selects the size of mapped RAM. If the size of the external memory is larger, a bus fault
occurs. If the size of the external memory is smaller, it wraps (upper address bits unused):
0x0 256 bytes; lower address range: 0x00 to 0xFF
0x1 64KB; lower address range: 0x0000 to 0xFFFF
0x2 16MB; lower address range: 0x00.0000 to 0xFF.FFFF
0x3 512MB; lower address range: 0x000.0000 to 0x1FFF.FFFF
External RAM Address
Selects address mapping for external RAM area.
0x0 Not mapped.
0x1 At 0x6000.0000
0x2 At 0x8000.0000
0x3 Only to be used with Host Bus quad chip select. In quad chip select mode, CS0 maps to
0x6000.0000 and CS1 maps to 0x8000.0000
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SPRUHE8E – October 2012 – Revised November 2019
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