Data Transmit Registers (Dxr[1,2]); Data Receive Registers (Drr2 And Drr1); Data Transmit Registers (Dxr2 And Dxr1) - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Receive data (for 8-, 12-, or 16-bit data) or low part of receive data (for 20-, 24- or 32-bit data)

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

15.12.2.1 Data Travel From Data Receive Pins to the Registers

If the serial word length is 16 bits or smaller, receive data on the MDRx pin is shifted into receive shift

copied to DRR1, which can be read by the CPU or by the DMA controller. The RSRs and RBRs are not

accessible to the user.

If the serial word length is larger than 16 bits, receive data on the MDRx pin is shifted into both of the

receive shift registers (RSR2, RSR1) and then copied into both of the receive buffer registers (RBR2,

RBR1). The content of the RBRs is then copied into both of the DRRs, which can be read by the CPU or

by the DMA controller.

If companding is used during the copy from RBR1 to DRR1 (RCOMPAND = 10b or 11b), the 8-bit

compressed data in RBR1 is expanded to a left-justified 16-bit value in DRR1. If companding is disabled,

the data copied from RBR[1,2] to DRR[1,2] is justified and bit filled according to the RJUST bits.

15.12.3 Data Transmit Registers (DXR[1,2])

For transmission, the CPU or the DMA controller writes data to one or both of the data transmit registers

15-66). If the serial word length is 16 bits or smaller, only DXR1 is used. If the word length is

larger than 16 bits, both DXR1 and DXR2 are used and DXR2 holds the most significant bits. Each frame

of transmit data in the McBSP can have one phase or two phases, each with its own serial word length.

Transmit data (for 8-, 12-, or 16-bit data) or low part of receive data (for 20-, 24- or 32-bit data)

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

15.12.3.1 Data Travel From Registers to Data Transmit (DX) Pins

If the serial word length is 16 bits or fewer, data written to DXR1 is copied to transmit shift register 1

(XSR1). From XSR1, the data is shifted onto the DX pin one bit at a time. The XSRs are not accessible.

If the serial word length is more than 16 bits, data written to DXR1 and DXR2 is copied to both transmit

shift registers (XSR2, XSR1). From the XSRs, the data is shifted onto the DX pin one bit at a time.

If companding is used during the transfer from DXR1 to XSR1 (XCOMPAND = 10b or 11b), the McBSP

compresses the 16-bit data in DXR1 to 8-bit data in the μ-law or A-law format in XSR1. If companding is

disabled, the McBSP passes data from the DXR(s) to the XSR(s) without modification.

SPRUHE8E – October 2012 – Revised November 2019

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Figure 15-65. Data Receive Registers (DRR2 and DRR1)

High part of receive data (for 20-, 24- or 32-bit data)

Figure 15-66. Data Transmit Registers (DXR2 and DXR1)

High part of transmit data (for 20-, 24- or 32-bit data)

C28 Multichannel Buffered Serial Port (McBSP)

McBSP Registers

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