Dma Peripheral Identification 0 (Dmaperiphid0), Offset 0Xfe0; Dma Channel Map Assignment (Dmachmap3) Register; Dma Channel Map Assignment (Dmachmap3) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Figure 16-31. DMA Channel Map Assignment (DMACHMAP3) Register
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16-38. DMA Channel Map Assignment (DMACHMAP3) Register Field Descriptions
Bit Field
31-28
27-24
23-20
19-16
15-12
11-8
7-4
3-0

16.7.23 DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0

The DMAPeriphIDn registers are hard-coded, and the fields within the registers determine the reset
values.
SPRUHE8E – October 2012 – Revised November 2019
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Value Description
0 Channel 31 First Assignment
1 Channel 31 Second Assignment
2 Channel 31 Third Assignment
3 Reserved
0 Channel 30 First Assignment
1 Channel 30 Second Assignment
2 Channel 30 Third Assignment
3 Reserved
0 Channel 29 First Assignment
1 Channel 29 Second Assignment
2 Channel 29 Third Assignment
3 Reserved
0 Channel 28 First Assignment
1 Channel 28 Second Assignment
2 Channel 28 Third Assignment
3 Reserved
0 Channel 27 First Assignment
1 Channel 27 Second Assignment
2 Channel 27 Third Assignment
3 Reserved
0 Channel 26 First Assignment
1 Channel 26 Second Assignment
2 Channel 26 Third Assignment
3 Reserved
0 Channel 25 First Assignment
1 Channel 25 Second Assignment
2 Channel 25 Third Assignment
3 Reserved
0 Channel 24 First Assignment
1 Channel 24 Second Assignment
2 Channel 24 Third Assignment
3 Reserved
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CHMAP3
R/W
M3 Micro Direct Memory Access ( µDMA)
µDMA Register Descriptions
0
1223