C28 Nmi Configuration (Cnmicfg) Register; C28 Nmi Configuration (Cnmicfg) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

www.ti.com

1.13.5.7 C28 NMI Configuration (CNMICFG) Register

NOTE: Clearing all latched NMI error flag conditions will stop the NMI watchdog counter and reset
it. Any new error condition that is latched will restart the counter.
The user should clear the NMI interrupt flag and clear all flags together to generate a new
interrupt if a new error event occurs.
15
Reserved
R-0:0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-78. C28 NMI Configuration (CNMICFG) Register Field Descriptions
Bit Field
15-7 Reserved
6 ACIBERRE
5 C28BISTERR
4 M3BISTERR
3-1 Reserved
0 CNMIE
1.13.5.8 C28 NMI Flag (CNMIFLG) Register
NOTE: The C28NMIFLG register is only reset by the XRS signal and not the C28 SYSRS signal.
This is so the cause of the particular reset condition can be identified.
SPRUHE8E – October 2012 – Revised November 2019
Submit Documentation Feedback
Figure 1-67. C28 NMI Configuration (CNMICFG) Register
7 6
ACIBERRE
R/W-0
Value Description
Reserved
ACIBERR NMI Enable
This enables the ACIBERR NMI condition to generate an NMI interrupt to the C28 CPU. Once
enabled, the bit cannot be cleared by the user. Only a device reset causing C28 SYSRSn reset will
clear the bit. Writes of 0 are ignored. Reading the bit will indicate if the ACIBERR NMI is enabled or
disabled.
Note: The ACIBERR NMI condition needs to be disabled at reset.
0 ACIBERR NMI disabled
1 ACIBERR NMI enabled
HW BIST Error NMI Flag: This bit indicates if the time out error or a signature mismatch error
condition during hardware BIST of C28 occurred. This bit can only be cleared by the user writing to
the corresponding clear bit in the NMIFLGCLR register or by an XRSn reset:
0 No C28 HWBIST error condition pending
1 C28 BIST error condition generated
HW BIST Error NMI Flag: This bit indicates if the time out error or a signature mismatch error
condition during hardware BIST of M3 occurred. This bit can only be cleared by the user writing to
the corresponding clear bit in the NMIFLGCLR register or by an XRSn reset:
0 No M3 HWBIST error condition pending
1 M3 BIST error condition generated
Reserved
NMI Enable
This bit when set to '1', meaning any condition, will generate an NMI interrupt to the C28x CPU and
kick off the NMI watchdog counter. As part of the boot sequence, this bit will be set to '1' by the
boot ROM. This is a write once bit, once set it cannot be cleared until system reset.
0 NMI disabled
1 NMI enabled
Copyright © 2012–2019, Texas Instruments Incorporated
5 4
C28BISTERR M3BISTERR
R/W-1 R/W-1
System Control and Interrupts
System Control Registers
3 1 0
Reserved CNMIE
R-0 R/W-x
207