Software Reset Control 2 (Srcr2) Register; Software Reset Control 2 (Srcr2) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Table 1-66. Software Reset Control 1 (SRCR1) Register Field Descriptions (continued)
Bit Field
6 SSI2
5 SSI1
4 SSI0
3 UART3
2 UART2
1 UART1
0 UART0

1.13.3.7 Software Reset Control 2 (SRCR2) Register

NOTE: Writes to this register are masked by the DC4 register.
Putting the module into reset and bringing it out of reset is done by software. When a
particular bit is set, the module goes into reset and to bring the module out of reset, software
has to again write a '0' explicitly to the register.
31
Reserved
R-0
23
15 14
Reserved
R-0
7 6
GPIOH GPIOG
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-67. Software Reset Control 2 (SRCR2) Register Field Descriptions
Bit Field
31-29 Reserved
28 EMAC0
27-17 Reserved
SPRUHE8E – October 2012 – Revised November 2019
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Value Description
SSI2 S/W Reset Control
When this bit is set, SSI2 is reset. All internal data is lost and the registers are returned to their
reset states. This bit must be manually cleared after being set.
SSI1 S/W Reset Control
When this bit is set, SSI1 is reset. All internal data is lost and the registers are returned to their
reset states. This bit must be manually cleared after being set.
SSI0 S/W Reset Control
When this bit is set, SSI0 is reset. All internal data is lost and the registers are returned to their
reset states. This bit must be manually cleared after being set.
UART3 S/W Reset Control
When this bit is set, UART3 is reset. All internal data is lost and the registers are returned to their
reset states. This bit must be manually cleared after being set.
UART2 S/W Reset Control
When this bit is set, UART2 is reset. All internal data is lost and the registers are returned to their
reset states. This bit must be manually cleared after being set.
UART1 S/W Reset Control
When this bit is set, UART1 is reset. All internal data is lost and the registers are returned to their
reset states. This bit must be manually cleared after being set.
UART0 S/W Reset Control
When this bit is set, UART0 is reset. All internal data is lost and the registers are returned to their
reset states. This bit must be manually cleared after being set.
Figure 1-56. Software Reset Control 2 (SRCR2) Register
29 28
EMAC0
R/W-0
Reserved
R-0
13 12
µDMA
R/W-0
5 4
GPIOF GPIOE
R/W-0 R/W-0
Value Description
Reserved
EMAC0 S/W Reset Control
When this bit is set, EMAC is reset. All internal data is lost and the registers are returned to their
reset states. This bit must be manually cleared after being set.
Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
27
Reserved
R-0
Reserved
R-0
3 2
GPIOD GPIOC
R/W-0 R/W-0
System Control and Interrupts
System Control Registers
24
17 16
USB
R/W-0
9 8
GPIOJ
R/W-0
1 0
GPIOB GPIOA
R/W-0 R/W-0
197