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15.12.4.2 Serial Port Control 2 Register (SPCR2)
The serial port control 2 register (SPCR2) is shown in
15
7
6
FRST
GRST
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15-73. Serial Port Control 2 Register (SPCR2) Field Descriptions
Bit
Field
Value
15-10
Reserved
0
9
FREE
8
SOFT
7
FRST
0
1
6
GRST
0
1
SPRUHE8E – October 2012 – Revised November 2019
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Figure 15-68. Serial Port Control 2 Register (SPCR2)
Reserved
R-0
5
4
XINTM
R/W-0
Description
Reserved bits (not available for your use). They are read-only bits and return 0s when read.
Free run bit. When a breakpoint is encountered in the high-level language debugger, FREE determines
whether the McBSP transmit and receive clocks continue to run or whether they are affected as
determined by the SOFT bit. When one of the clocks stops, the corresponding data transfer
(transmission or reception) stops.
Soft stop bit. When FREE = 0, SOFT determines the response of the McBSP transmit and receive
clocks when a breakpoint is encountered in the high-level language debugger. When one of the clocks
stops, the corresponding data transfer (transmission or reception) stops.
Frame-synchronization logic reset bit. The sample rate generator of the McBSP includes frame-
synchronization logic to generate an internal frame-synchronization signal. You can use FRST to take
the frame-synchronization logic into and out of its reset state. This bit has a negative polarity; FRST =
0 indicates the reset state.
If you read a 0, the frame-synchronization logic is in its reset state.
If you write a 0, you reset the frame-synchronization logic.
In the reset state, the frame-synchronization logic does not generate a frame-synchronization signal
(FSG).
If you read a 1, the frame-synchronization logic is enabled.
If you write a 1, you enable the frame-synchronization logic by taking it out of its reset state.
When the frame-synchronization logic is enabled (FRST = 1) and the sample rate generator as a
whole is enabled (GRST = 1), the frame-synchronization logic generates the frame-synchronization
signal FSG as programmed.
Sample rate generator reset bit. You can use GRST to take the McBSP sample rate generator into and
out of its reset state. This bit has a negative polarity; GRST = 0 indicates the reset state.
To read about the effects of a sample rate generator reset, see
Initializing a McBSP.
If you read a 0, the sample rate generator is in its reset state.
If you write a 0, you reset the sample rate generator.
If GRST = 0 due to a reset, CLKG is driven by the CPU clock divided by 2, and FSG is driven low
(inactive). If GRST = 0 due to program code, CLKG and FSG are both driven low (inactive).
If you read a 1, the sample rate generator is enabled.
If you write a 1, you enable the sample rate generator by taking it out of its reset state.
When enabled, the sample rate generator generates the clock signal CLKG as programmed in the
sample rate generator registers. If FRST = 1, the generator also generates the frame-synchronization
signal FSG as programmed in the sample rate generator registers.
Copyright © 2012–2019, Texas Instruments Incorporated
Figure 15-68
and described in
10
3
2
XSYNCERR
XEMPTY
R/W-0
R-0
Section
C28 Multichannel Buffered Serial Port (McBSP)
McBSP Registers
Table
15-73.
9
8
FREE
SOFT
R/W-0
R/W-0
1
0
XRDY
XRST
R-0
R/W-0
15.10.2, Resetting and
1161
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