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McBSP Sample Rate Generator
15.4.2 Frame Synchronization Generation in the Sample Rate Generator
The sample rate generator can produce a frame-synchronization signal (FSG) for use by the receiver, the
transmitter, or both.
If you want the receiver to use FSG for frame synchronization, make sure FSRM = 1. (When FSRM = 0,
receive frame synchronization is supplied via the FSR pin.)
If you want the transmitter to use FSG for frame synchronization, you must set:
•
FSXM = 1 in PCR: This indicates that transmit frame synchronization is supplied by the McBSP itself
rather than from the FSX pin.
•
FSGM = 1 in SRGR2: This indicates that when FSXM = 1, transmit frame synchronization is supplied
by the sample rate generator. (When FSGM = 0 and FSXM = 1, the transmitter uses frame-
synchronization pulses generated every time data is transferred from DXR[1,2] to XSR[1,2].)
In either case, the sample rate generator must be enabled (GRST = 1) and the frame-synchronization
logic in the sample rate generator must be enabled (FRST = 0).
15.4.2.1 Choosing the Width of the Frame-Synchronization Pulse on FSG
Each pulse on FSG has a programmable width. You program the FWID bits of SRGR1, and the resulting
pulse width is (FWID + 1) CLKG cycles, where CLKG is the output clock of the sample rate generator.
15.4.2.2 Controlling the Period Between the Starting Edges of Frame-Synchronization Pulses on FSG
You can control the amount of time from the starting edge of one FSG pulse to the starting edge of the
next FSG pulse. This period is controlled in one of two ways, depending on the configuration of the
sample rate generator:
•
If the sample rate generator is using an external input clock and GSYNC = 1 in SRGR2, FSG pulses in
response to an inactive-to-active transition on the FSR pin. Thus, the frame-synchronization period is
controlled by an external device.
•
Otherwise, you program the FPER bits of SRGR2, and the resulting frame-synchronization period is
(FPER + 1) CLKG cycles, where CLKG is the output clock of the sample rate generator.
15.4.2.3 Keeping FSG Synchronized to an External Clock
When an external signal is selected to drive the sample rate generator (see
Section
15.4.1.2), the GSYNC bit of SRGR2 and the FSR pin can be used to configure the timing of FSG
pulses.
GSYNC = 1 ensures that the McBSP and an external device are dividing down the input clock with the
same phase relationship. If GSYNC = 1, an inactive-to-active transition on the FSR pin triggers a
resynchronization of CLKG and generation of FSG.
See
Section 15.4.3
15.4.3 Synchronizing Sample Rate Generator Outputs to an External Clock
The sample rate generator can produce a clock signal (CLKG) and a frame-synchronization signal (FSG)
based on an input clock signal that is either the CPU clock signal or a signal at the MCLKR or MCLKX pin.
When an external clock is selected to drive the sample rate generator, the GSYNC bit of SRGR2 and the
FSR pin can be used to control the timing of CLKG and the pulsing of FSG relative to the chosen input
clock.
Make GSYNC = 1 when you want the McBSP and an external device to divide down the input clock with
the same phase relationship. If GSYNC = 1:
•
An inactive-to-active transition on the FSR pin triggers a resynchronization of CLKG and a pulsing of
FSG.
•
CLKG always begins with a high state after synchronization.
•
FSR is always detected at the same edge of the input clock signal that generates CLKG, no matter
how long the FSR pulse is.
1090
C28 Multichannel Buffered Serial Port (McBSP)
for more details about synchronization.
Copyright © 2012–2019, Texas Instruments Incorporated
Section 15.4.1.2
SPRUHE8E – October 2012 – Revised November 2019
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