Texas Instruments Concerto F28M36 Series Technical Reference Manual page 9

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11.8.18 Source/Destination Wrap Step Size Registers (SRC/DST_WRAP_STEP) - EALLOW Protected
11.8.19 Shadow Source Begin and Current Address Pointer Registers
(SRC_BEG_ADDR_SHADOW/DST_BEG_ADDR_SHADOW) - All EALLOW Protected
11.8.20 Active Source Begin and Current Address Pointer Registers
(SRC_BEG_ADDR/DST_BEG_ADDR)
11.8.21 Shadow Destination Begin and Current Address Pointer Registers
(SRC_ADDR_SHADOW/DST_ADDR_SHADOW) - All EALLOW Protected
11.8.22 Active Destination Begin and Current Address Pointer Registers (SRC_ADDR/DST_ADDR)
12 C28 Serial Peripheral Interface (SPI)
12.1 Enhanced SPI Module Overview
12.1.1 SPI Block Diagram
12.1.2 SPI Module Signal Summary
12.1.3 Overview of SPI Module Registers
12.1.4 SPI Operation
12.1.5 SPI Interrupts
12.1.6 SPI FIFO Description
12.1.7 SPI 3-Wire Mode Description
12.1.8 SPI STEINV Bit in Digital Audio Transfers
12.2 C28 SPI-A to M3 SSI3 Internal Loopback
12.2.1 Loopback Initialization and Configuration
12.3 SPI Registers and Waveforms
12.3.1 SPI Control Registers
12.3.2 SPI Example Waveforms
13 C28 Serial Communications Interface (SCI)
13.1 Enhanced SCI Module Overview
13.1.1 Architecture
13.2 C28 SCI-A to M3 UART4 Internal Loopback
13.2.1 Loopback Initialization and Configuration
13.3 SCI Registers
13.3.1 SCI Module Register Summary
13.3.2 SCI Communication Control Register (SCICCR)
13.3.3 SCI Control Register 1 (SCICTL1)
13.3.4 SCI Baud-Select Registers (SCIHBAUD, SCILBAUD)
13.3.5 SCI Control Register 2 (SCICTL2)
13.3.6 SCI Receiver Status Register (SCIRXST)
13.3.7 Receiver Data Buffer Registers (SCIRXEMU, SCIRXBUF)
13.3.8 SCI Transmit Data Buffer Register (SCITXBUF)
13.3.9 SCI FIFO Registers (SCIFFTX, SCIFFRX, SCIFFCT)
13.3.10 Priority Control Register (SCIPRI)
14 C28 Inter-Integrated Circuit Module
14.1 Introduction to the I2C Module
14.1.1 Features
14.1.2 Features Not Supported
14.1.3 Functional Overview
14.1.4 Clock Generation
14.2 I2C Module Operational Details
14.2.1 Input and Output Voltage Levels
14.2.2 Data Validity
14.2.3 Operating Modes
14.2.4 I2C Module START and STOP Conditions
14.2.5 Serial Data Formats
14.2.6 NACK Bit Generation
14.2.7 Clock Synchronization
SPRUHE8E - October 2012 - Revised November 2019
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Copyright © 2012-2019, Texas Instruments Incorporated
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