Flash Module Controller (Fmc); Flash And Otp Automatic Power-Down Modes; Fmc Interface With Core, Bank And Pump - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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M3 OTP location
0x68101C

5.3.5 Flash Module Controller (FMC)

There is a dedicated flash module controller in both the master subsystem (M3-FMC) and the control
subsystem (C28x-FMC). The Cortex M3 core in the master subsystem interfaces with the M3 flash module
controller (M3-FMC), which in turn, interfaces with the M3 flash bank and shared pump to perform
erase/program operations as well as to read data/execute code from the M3 flash bank.
The C28x core in the control subsystem interfaces with the C28x flash module controller (C28x-FMC)
which in turn, interfaces with the C28x flash bank and shared pump to perform erase/program operations
as well as to read data/execute code from the C28x flash bank. Control signals to the flash pump will be
controlled by either C28x-FMC or M3-FMC, depending on who gains the flash pump semaphore.
There is a state machine in both M3-FMC and C28x-FMC which generates the erase/program sequences
in hardware. This simplifies the Flash API software (refer to the C2000 F021 Application Programming
Interface (API) Reference Guide, SPNU595, for details on Flash API) which configures control registers in
FMC to perform flash erase and program operations.
The following sections
describe FMC in detail.

5.3.6 Flash and OTP Automatic Power-Down Modes

The flash bank and pump consume a significant amount of power when active. The flash module provides
a mechanism to automatically power-down flash banks after they have not been accessed for some user-
programmable time. Special timers automatically sequence the power-up and power-down of the M3 flash
bank and C28x flash bank independently of each other. The shared charge pump module has its own
independent power up/down timers as well.
SPRUHE8E – October 2012 – Revised November 2019
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Table 5-90. Programmable OTP Locations in M3 OTP (continued)
Field name
MAIN_OSC_CLK_FREQ
Figure 5-81. FMC Interface with Core, Bank and Pump
C28x System Clock
C28x Core
Cortex-M3
M3 System Clock
(Section 5.3.6, Section
Copyright © 2012–2019, Texas Instruments Incorporated
Field description
Input MAINOSC frequency connected to the
device. M-Boot ROM reads this location to
know the MAINOSC frequency to configure
the management clock divider for 2.5 MHz
for EMAC boot mode.
C28x-Bank
C28-FMC
Pump
M3-FMC
PUMP SEMAPHORE
M3-Bank
5.3.8, Section 5.3.8, Section
Flash Controller Memory Module
Size (bytes)
4
5.3.9, and Section 5.3.10) will
Internal Memory
537