I2C Bus Configuration; Start And Stop Conditions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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22.3.1 I2C Bus Functional Overview
The I2C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL. SDA is the bi-directional
serial data line and SCL is the bi-directional serial clock line. The bus is considered idle when both lines
are high.
Every transaction on the I2C bus is nine bits long, consisting of eight data bits and a single acknowledge
bit. The number of bytes per transfer (defined as the time between a valid START and STOP condition,
described in Section
data must be transferred MSB first. When a receiver cannot receive another complete byte, it can hold the
clock line SCL Low and force the transmitter into a wait state. The data transfer continues when the
receiver releases the clock SCL.

22.3.1.1 START and STOP Conditions

The protocol of the I2C bus defines two states to begin and end a transaction: START and STOP. A high-
to-low transition on the SDA line while the SCL is high is defined as a START condition, and a low-to-high
transition on the SDA line while SCL is high is defined as a STOP condition. The bus is considered busy
after a START condition and free after a STOP condition. See
The STOP bit determines if the cycle stops at the end of the data cycle or continues on to a repeated
START condition. To generate a single transmit cycle, the I2C Master Slave Address (I2CMSA) register is
written with the desired address, the R/S bit is cleared, and the Control register is written with ACK=X (0
or 1), STOP=1, START=1, and RUN=1 to perform the operation and stop. When the operation is
completed (or aborted due an error), the interrupt pin becomes active and the data may be read from the
I2C Master Data (I2CMDR) register. When the I2C module operates in Master receiver mode, the ACK bit
is normally set causing the I2C bus controller to transmit an acknowledge automatically after each byte.
This bit must be cleared when the I2C bus controller requires no further data to be transmitted from the
slave transmitter.
When operating in slave mode, two bits in the I2C Slave Raw Interrupt Status (I2CSRIS) register indicate
detection of start and stop conditions on the bus; while two bits in the I2C Slave Masked Interrupt Status
(I2CSMIS) register allow start and stop conditions to be promoted to controller interrupts (when interrupts
are enabled).
22.3.1.2 Data Format with 7-Bit Address
Data transfers follow the format shown in
transmitted. This address is 7-bits long followed by an eighth bit, which is a data direction bit (R/S bit in
the I2CMSA register). If the R/S bit is clear, it indicates a transmit operation (send), and if it is set, it
indicates a request for data (receive). A data transfer is always terminated by a STOP condition generated
by the master, however, a master can initiate communications with another device on the bus by
generating a repeated START condition and addressing another slave without first generating a STOP
condition. Various combinations of receive/transmit formats are then possible within a single transfer.
SPRUHE8E – October 2012 – Revised November 2019
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Figure 22-2. I2C Bus Configuration
R PUP
SCL
SDA
I2CSCL I2CSDA
Concerto
22.3.1.1, is unrestricted, but each byte has to be followed by an acknowledge bit, and
Figure 22-3. START and STOP Conditions
SDA
SCL
START
condition
Figure
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R PUP
I 2 C Bus
SCL SDA SCL SDA
3rd Party Device 3rd Party Device
with I 2 C Interface with I 2 C Interface
Figure 22-3.
SDA
SCL
STOP
condition
22-4. After the START condition, a slave address is
M3 Inter-Integrated Circuit (I2C) Interface
Functional Description
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