M0, M1 And C28T0C28_Msg_Ram Test And Initialization Register (C28Rtestinit); M0, M1 And C28T0C28_Msg_Ram Test And Initialization Register (C28Rtestinit) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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RAM Control Module Registers

M0, M1 and C28T0C28_MSG_RAM Test and Initialization Register (C28RTESTINIT)

Figure 5-50. M0, M1 and C28T0C28_MSG_RAM Test and Initialization Register (C28RTESTINIT)

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-59. M0, M1 and C28T0C28_MSG_RAM Test and Initialization Register (C28RTESTINIT) Field

ECCPARTESTM1

ECCPARTESTM0

Internal Memory

Enable/Disable RAMTEST Feature for CTOM_MSG_RAM

RAMTEST feature is disabled for CTOM_MSG_RAM block.

RAMTEST feature is enabled for CTOM_MSG_RAM block. ECC/parity logic is bypassed for

memory accesses.

RAM Initialization for CTOM_MSG_RAM Block. Any reads to this bit will return a 0.

No action taken.

Initialize all address locations of CTOM_MSG_RAM block with data 0x0 and corresponding data an

address ECC/parity bits.

Enable/Disable RAMTEST Feature for M1 RAM Block

RAMTEST feature is disabled for M1 RAM block.

RAMTEST feature is enabled for M1 RAM block. ECC/parity logic is bypassed for memory

RAM Initialization M1. Any reads to this bit will return a 0.

No action taken.

Initialize all address locations of M1 RAM block with data 0x0 and corresponding data an address

ECC/parity bits.

Enable/Disable RAMTEST Feature for M0 RAM Block

RAMTEST feature is disabled for M0 RAM block.

RAMTEST feature is enabled for M0 RAM block. ECC/parity logic is bypassed for memory

RAM Initialization M0. Any reads to this bit will return a 0.

No action taken.

Initialize all address locations of M0 RAM block with data 0x0 and corresponding data an address

ECC/parity bits.

Descriptions

SPRUHE8E – October 2012 – Revised November 2019

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