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RAM Control Module
Cycle
Cycle #3
Cycle #4
Cycle #5
Cycle #6
Cycle #7
Cycle
Cycle #1
Cycle #2
Cycle #3
Cycle #4
Cycle #5
Cycle
Cycle #1
Cycle #2
Cycle #3
Cycle #4
Cycle #5
Cycle #6
Cycle #7
Cycle #8
Following are some guidelines to follow while allocating code into any of the Sx RAM blocks:
•
For least latency on the re-locatable NVIC vector table accesses for exception accesses, user should
allocate the vector tables in a dedicated RAM block.
•
In case of bit-band writes from the M3 CPU, it is possible that the latency for C28 accesses to shared
memories will increase, depending on the M3 CPU bit-banded accesses. Users must ensure that they
partition application memory such that the effect of this does not affect C28 real-time performance
requirements.
5.1.1.5
Access Timing
In general on these devices, all RAM blocks have one cycle access time; that is, if there is only one
access and no other access is pending to that particular RAM block. However, since there are different
types of shared RAMs, where multiple masters can access the same RAM block, that will not always be
the case.
Following are access cycle times in different scenarios:
•
In case of M3/µDMA, a write access, immediately followed by a read access to the same RAM block,
incurs a stall of a single clock cycle.
•
M3/µDMA write access can have one extra wait state in case of arbitration and M3/µDMA access does
not win during arbitration cycle.
•
Max cycle latency for an access to Sx memory from any master is five cycles when M3 is master for
that Sx memory. The following are the possible accesses with details of how many cycles each access
466
Internal Memory
Table 5-3. Extra Wait State (continued)
Accesses
No Access
Master1 Access
Master2 Access
No Access
No Access
Table 5-4. Round-Robin Exception
Accesses
Master1 Access
Master 1 Access/Master2 Access
Master1 Access
No Access
No Access
Table 5-5. C28x-CPU, Fixed Priority
Accesses
M3 Access
C28x PRd Access/C28x DWr
Access/DMA Access
C28x DRd Access/uDMA Access
No Access
M3 Access
No Access
No Access
No Access
Copyright © 2012–2019, Texas Instruments Incorporated
Access Granted
Master2 Access
Idle
Master1 Access
Master2 Access
Idle
Access Granted
Master1 Access
Master1 Access
Master2 Access
Master1 Access
Idle
Access Granted
M3 Access
Idle
C28x DWr Access
DMA Access
uDMA Access
M3 Access
C28x DRd access
C28x PRd access
SPRUHE8E – October 2012 – Revised November 2019
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