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Table 14-10. I2C Status Register (I2CSTR) Field Descriptions (continued)
Bit
Field
0
AL
The I2C peripheral cannot detect a START or STOP condition when it is in reset, i.e. the IRS bit is set to
0. Therefore, the BB bit will remain in the state it was at when the peripheral was placed in reset. The BB
bit will stay in that state until the I2C peripheral is taken out of reset, i.e. the IRS bit is set to 1, and a
START or STOP condition is detected on the I2C bus.
Follow these steps before initiating the first data transfer with I2C :
1. After taking the I2C peripheral out of reset by setting the IRS bit to 1, wait a certain period to detect the
actual bus status before starting the first data transfer. Set this period larger than the total time taken
for the longest data transfer in the application. By waiting for a period of time after I2C comes out of
reset, users can ensure that at least one START or STOP condition will have occurred on the I2C bus,
and been captured by the BB bit. After this period, the BB bit will correctly reflect the state of the I2C
bus.
2. Check the BB bit and verify that BB=0 (bus not busy) before proceeding.
3. Begin data transfers.
Not resetting the I2C peripheral in between transfers ensures that the BB bit reflects the actual bus status.
If users must reset the I2C peripheral in between transfers, repeat steps 1 through 3 every time the I2C
peripheral is taken out of reset.
14.5.5 I2C Interrupt Source Register (I2CISRC)
The I2C interrupt source register (I2CISRC) is a 16-bit register used by the CPU to determine which event
generated the I2C interrupt. For more information about these events, see the descriptions of the I2C
interrupt requests in
15
12
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-11. I2C Interrupt Source Register (I2CISRC) Field Descriptions
Bit
Field
15-12
Reserved
11-8
Reserved
7-3
Reserved
SPRUHE8E – October 2012 – Revised November 2019
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Value
Description
Arbitration-lost interrupt flag bit (only applicable when the I2C module is a master-transmitter). AL
primarily indicates when the I2C module has lost an arbitration contest with another master-
transmitter. The CPU can poll AL or use the AL interrupt request (see
0
Arbitration not lost. AL is cleared by any one of the following events:
• AL is manually cleared. To clear this bit, write a 1 to it.
• The CPU reads the interrupt source register (I2CISRC) and the register contains the code for an
AL interrupt. Emulator reads of the I2CISRC do not affect this bit.
• The I2C module is reset.
1
Arbitration lost. AL is set by any one of the following events:
• The I2C module senses that it has lost an arbitration with two or more competing transmitters
that started a transmission almost simultaneously.
• The I2C module attempts to start a transfer while the BB (bus busy) bit is set to 1.
When AL becomes 1, the MST and STP bits of I2CMDR are cleared, and the I2C module becomes
a slave-receiver.
Table
14-3.
Figure 14-20. I2C Interrupt Source Register (I2CISRC)
11
Reserved
R/W-0
Value
Description
These reserved bit locations are always read as zeros. A value written to this field has no effect.
These reserved bit locations should always be written as zeros.
These reserved bit locations are always read as zeros. A value written to this field has no effect.
Copyright © 2012–2019, Texas Instruments Incorporated
8
7
Reserved
R-0
I2C Module Registers
Section
14.3.1)
3
2
INTCODE
R-0
C28 Inter-Integrated Circuit Module
0
1065
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