M0, M1 And C28T0M3_Msg_Ram Init Done Register (C28Rinitdone); M0, M1 And C28T0M3_Msg_Ram Init Done Register (C28Rinitdone) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

RAM Control Module Registers

5.2.3.10 M0, M1 and C28T0M3_MSG_RAM INIT Done Register (C28RINITDONE)

Figure 5-53. M0, M1 and C28T0M3_MSG_RAM INIT Done Register (C28RINITDONE)
31
7
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-62. M0, M1 and C28T0M3_MSG_RAM INIT Done Register (C28RINITDONE) Field
Bit Field
31-5 Reserved
4 RAMINITDONEC
TO
MMSGRAM
3 Reserved
2 RAMINITDONEM
1
1 Reserved
0 RAMINITDONEM
0
518
Internal Memory
5 4
RAMINITDONE
CTO
MMSGRAM
R-0
Value Description
Reserved
RAM Initialization Process Status when RAMINIT is Set for CTOM_MSG_RAM Block
RAM initialization is not finished for CTOM_MSG_RAM block.
0 RAM initialization is done for CTOM_MSG_RAM block. CTOM_MSG_RAM can be accessed by M3
CPU/µDMA.
1 This status bit gets cleared when the RAMINIT bit is set for C0 RAM block.
Reserved
RAM Initialization Process Status when RAMINIT is Set for M1 RAM Block
RAM initialization is not finished for M1 RAM block.
0 RAM initialization is done for M1 RAM block. M1 RAM can be accessed by M3 CPU.
1 This status bit gets cleared when the RAMINIT bit is set for M1 RAM block.
Reserved
RAM Initialization Process Status when RAMINIT is Set for M0 RAM Block
RAM initialization is not finished for M0 RAM block.
0 RAM initialization is done for M0 RAM block. M0 RAM can be accessed by M3 CPU.
1 This status bit gets cleared when the RAMINIT bit is set for M0 RAM block.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
3 2
RAMINITDONE
Reserved
M1
R-0 R-0
Descriptions
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
8
1 0
RAMINITDONE
Reserved
M0
R-0 R-0
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