Application Interrupt And Reset Control (Apint) Register; Interrupt Priority Levels; Application Interrupt And Reset Control (Apint) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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25.6.5 Application Interrupt and Reset Control (APINT) Register, offset 0xD0C
The Application Interrupt and Reset Control (APINT) register provides priority grouping control for the
exception model, endian status for data accesses, and reset control of the system. To write to this
register, 0x05FA must be written to the VECTKEY field, otherwise the write is ignored.
The PRIGROUP field indicates the position of the binary point that splits the INTx fields in the Interrupt
Priority (PRIx) registers into separate group priority and subpriority fields.
PRIGROUP value controls this split. The bit numbers in the Group Priority Field and Subpriority Field
columns in the table refer to the bits in the INTA field. For the INTB field, the corresponding bits are 15:13;
for INTC, 23:21; and for INTD, 31:29.
Note: This register can only be accessed from privileged mode.
Note: Determining preemption of an exception uses only the group priority field.
PRIGROUP Bit
Field
0x0 - 0x4
0x5
0x6
0x7
(1)
INTx field showing the binary point. An x denotes a group priority field bit, and a y denotes a subpriority field bit.
Figure 25-36. Application Interrupt and Reset Control (APINT) Register
31
15 14
ENDIANESS Reserved
R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-43. Application Interrupt and Reset Control (APINT) Register Field Descriptions
Bit Field
31-16 VECTKEY
15 ENDIANESS
14-11 Reserved
10-8 PRIGROUP
7-3 Reserved
2 SYSRESREQ
1 VECTCLRACT
SPRUHE8E – October 2012 – Revised November 2019
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Table 25-42. Interrupt Priority Levels
(1)
Binary Point Group Priority
Field
bxxx. [7:5]
bxx.y [7:6]
bx.yy [7]
b.yyy None
11 10
PRIGROUP
R/W-0
Value Description
Register Key
This field is used to guard against accidental writes to this register. 0x05FA must be written to this
field in order to change the bits in this register.
On a read, 0xFA05 is returned.
Data Endianess
This implementation uses only little-endian mode so this is cleared to 0.
Reserved
Interrupt Priority Grouping
This field determines the split of group priority from subpriority (see
information).
Reserved
System Reset Request
0 No effect
1 Resets the core and all on-chip peripherals except the Debug interface.
This bit is automatically cleared during the reset of the core and reads as 0.
Clear Active NMI / Fault
This bit is reserved for Debug use and reads as 0. This bit must be written as a 0, otherwise
behavior is unpredictable.
Copyright © 2012–2019, Texas Instruments Incorporated
System Control Block (SCB) Register Descriptions
Subpriority Field
None
[5]
[6:5]
[7:5]
VECTKEY
R/W-FA05h
8 7 3
Reserved SYSRESREQ
R-0 W-0
Table 25-42 shows how the
Group Priorities Subpriorities
8
4
2
1
2 1
VECTCLRACT VECTRESET
W-0
Table 25-42 for more
Cortex-M3 Peripherals
1
2
4
8
16
0
W-0
1671