Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Concerto F28M35x

Technical Reference Manual

Literature Number: SPRUH22I

April 2012 – Revised November 2019

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Table of Contents

Summary of Contents for Texas Instruments Concerto F28M35 Series

Page 1 Concerto F28M35x Technical Reference Manual Literature Number: SPRUH22I April 2012 – Revised November 2019...
Page 2: Table Of Contents
1.10.2 CSM Impact on Other On-Chip Resources ............1.10.3 Incorporating Code Security in User Applications ..............1.10.4 Do's and Don'ts to Protect Security Logic Contents SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 3 GPTM Raw Interrupt Status (GPTMRIS) Register, offset 0x01C ........2.6.7 GPTM Masked Interrupt Status (GPTMMIS) Register, offset 0x020 ..........2.6.8 GPTM Interrupt Clear (GPTMICR) Register, offset 0x024 SPRUH22I – April 2012 – Revised November 2019 Contents Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 4 4.2.1 Introduction ..................4.2.2 GPIO Module Overview ..................4.2.3 Configuration Overview ................4.2.4 Digital General Purpose I/O Control ....................4.2.5 Input Qualification Contents SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 5 ..................6.5.15 M-Boot ROM Boot Modes ....................C-Boot ROM Description ..................6.6.1 C-Boot ROM Memory Map ................6.6.2 C-Boot ROM RAM Initialization SPRUH22I – April 2012 – Revised November 2019 Contents Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 6 PWM-Chopper Submodule Control Register ............7.4.6 Trip-Zone Submodule Control and Status Registers ............... 7.4.7 Digital Compare Submodule Registers ................7.4.8 GPTRIP Input Select Registers Contents SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 7 10.3.1 Features ....................10.3.2 Block Diagram ................... 10.3.3 SOC Principle of Operation ..............10.3.4 ONESHOT Single Conversion Support ..................10.3.5 ADC Conversion Priority SPRUH22I – April 2012 – Revised November 2019 Contents Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 8 11.8.14 Source Transfer Step Size Register (SRC_TRANSFER_STEP) — EALLOW Protected ..11.8.15 Destination Transfer Step Size Register (DST_TRANSFER_STEP) — EALLOW Protected ..11.8.16 Source/Destination Wrap Size Register (SRC/DST_WRAP_SIZE) — EALLOW protected) Contents SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 9 1012 ..............14.2.4 I2C Module START and STOP Conditions 1013 ................... 14.2.5 Serial Data Formats 1013 ..................14.2.6 NACK Bit Generation 1015 SPRUH22I – April 2012 – Revised November 2019 Contents Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 10 McBSP Exception/Error Conditions 1056 ....................15.5.1 Types of Errors 1056 ..................15.5.2 Overrun in the Receiver 1056 ............. 15.5.3 Unexpected Receive Frame-Synchronization Pulse 1058 Contents SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 11 15.9.9 Set the Transmit Frame Length 1103 ....... 15.9.10 Enable/Disable the Transmit Frame-Synchronization Ignore Function 1104 ..............15.9.11 Set the Transmit Companding Mode 1105 SPRUH22I – April 2012 – Revised November 2019 Contents Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 12 16.6.2 DMA Channel Destination Address End Pointer (DMADSTENDP), offset 0x004 1171 ..........16.6.3 DMA Channel Control Word (DMACHCTL), offset 0x008 1172 ................... 16.7 µDMA Register Descriptions 1175 Contents SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 13 17.7.4 Host Bus Operation 1212 ....................17.8 General-Purpose Mode 1215 ................17.8.1 General Purpose Bus Operation 1218 ..................... 17.9 C28x Access to EPI 1223 SPRUH22I – April 2012 – Revised November 2019 Contents Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 14 1279 ....................... 18.1 Introduction 1280 ....................18.1.1 Block Diagram 1280 ....................18.2 Functional Description 1280 ..................18.2.1 Operation as a Device 1281 Contents SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 15 18.5.37 USB Receive Control and Status Endpoint n Low Register (USBRXCSRL[1]- ....................USBRXCSRL[15]) 1345 18.5.38 USB Receive Control and Status Endpoint n High Register (USBRXCSRH[1]- SPRUH22I – April 2012 – Revised November 2019 Contents Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 16 19.6.14 Ethernet MAC Number of Packets (MACNP) Register, offset 0x034 1400 ......19.6.15 Ethernet MAC Transmission Request (MACTR) Register, offset 0x038 1401 Contents SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 17 21.7.6 UART Fractional Baud-Rate Divisor Register (UARTFBRD), offset 0x028 1467 ..........21.7.7 UART Line Control Register (UARTLCRH), offset 0x02C 1467 ............21.7.8 UART Control Register (UARTCTL), offset 0x030 1468 SPRUH22I – April 2012 – Revised November 2019 Contents Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 18 22.7.7 I2C Slave Interrupt Clear (I2CSICR), offset 0x818 1511 ..................M3 Controller Area Network (CAN) 1512 ......................... 23.1 Overview 1513 ....................... 23.1.1 Features 1513 Contents SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 19 23.15 CAN Control Registers 1543 ................. 23.15.1 CAN Control Register (CAN CTL) 1544 ..............23.15.2 Error and Status Register (CAN ES) 1546 SPRUH22I – April 2012 – Revised November 2019 Contents Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 20 24.7.6 Interrupt Priority Grouping 1590 .................. 24.7.7 Exception Entry and Return 1590 ......................24.8 Fault Handling 1592 ..................... 24.8.1 Fault Types 1592 Contents SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 21 ........... 25.6.4 Vector Table Offset (VTABLE) Register, offset 0xD08 1633 ......25.6.5 Application Interrupt and Reset Control (APINT) Register, offset 0xD0C 1634 SPRUH22I – April 2012 – Revised November 2019 Contents Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 22 25.7.4 MPU Region Base Address (MPUBASE) Register, Offset 0xD9c-0xDB4 1651 ......25.7.5 MPU Region Attribute and Size (MPUATTR) Register, offset 0xDA0-DB8 1652 ........................Revision History 1654 Contents SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 23 1-45. Control Subsystem Peripheral Configuration 3 (CCNF3) Register ..........1-46. Control Subsystem Peripheral Configuration 4 (CCNF4) Register ........... 1-47. Master Subsystem Memory Configuration (MEMCNF) Register SPRUH22I – April 2012 – Revised November 2019 List of Figures Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 24 1-94. System Clock Divider (SYSDIVSEL) Register ..............1-95. System PLL Lock Status (SYSPLLSTS) Register ............1-96. Master Subsystem Clock Divider (M3SSDIVSEL) Register List of Figures SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 25 ....................1-141. Z1_GRABRAMR Register ..................... 1-142. Z2_GRABSECTR Register ....................1-143. Z2_GRABRAMR Register ....................1-144. Z1_EXEONLYR Register ....................1-145. Z2_EXEONLYR Register SPRUH22I – April 2012 – Revised November 2019 List of Figures Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 26 2-9. GPTM Control (GPTMCTL) Register ................2-10. GPTM Interrupt Mask (GPTMIMR) Register ..............2-11. GPTM Raw Interrupt Status (GPTMRIS) Register List of Figures SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 27 4-12. GPIO Interrupt Clear (GPIOICR) Register ............4-13. GPIO Alternate Function Select (GPIOAFSEL) Register ..............4-14. GPIO Open Drain Select (GPIOODR) Register SPRUH22I – April 2012 – Revised November 2019 List of Figures Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 28 4-61. GPIO Port B Direction (GPBDIR) Register ................4-62. GPIO Port C Direction (GPCDIR) Register ................4-63. GPIO Port E Direction (GPEDIR) Register List of Figures SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 29 5-32. Non-Master Access Violation Flag Clear Register (MNMAVCLR) ..............5-33. Master Access Violation Flag Register (MMAVFLG) ............5-34. Master Access Violation Flag Clear Register (MMAVCLR) SPRUH22I – April 2012 – Revised November 2019 List of Figures Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 30 5-81. ECC Logic Inputs and Outputs ................5-82. Flash Read Control Register (FRDCNTL) ............... 5-83. Flash Read Margin Control Register (FSPRD) List of Figures SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 31 ................5-130. Data Low Test Register (FDATAL_TEST) ................. 5-131. ECC Test Address Register (FADDR_TEST) ..................5-132. ECC Test Register (FECC_TEST) SPRUH22I – April 2012 – Revised November 2019 List of Figures Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 32 ............. 7-3. ePWM Submodules and Critical Internal Signal Interconnects ....................7-4. Time-Base Submodule ................ 7-5. Time-Base Submodule Signals and Registers List of Figures SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 33 7-45. Event-Trigger SOCA Pulse Generator ................. 7-46. Event-Trigger SOCB Pulse Generator ............7-47. Digital-Compare Submodule High-Level Block Diagram .................. 7-48. GPIO MUX-to-Trip Input Connectivity SPRUH22I – April 2012 – Revised November 2019 List of Figures Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 34 7-94. Counter-Compare B Register (CMPB) ................. 7-95. Counter-Compare C Register (CMPC) ................. 7-96. Counter-Compare D Register (CMPD) ..............7-97. Compare B High-Resolution Register (CMPBHR) List of Figures SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 35 Capture Function Diagram ....................8-4. Event Prescale Control ..................8-5. Prescale Function Waveforms ................8-6. Details of the Continuous/One-shot Block SPRUH22I – April 2012 – Revised November 2019 List of Figures Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 36 9-26. eQEP Position Counter Initialization (QPOSINIT) Register ..........9-27. eQEP Maximum Position Count Register (QPOSMAX) Register ..............9-28. eQEP Position-compare (QPOSCMP) Register List of Figures SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 37 10-32. ADC SOC Flag 1 Register (ADCSOCFLG1) (Address Offset 18h) ..........10-33. ADC SOC Force 1 Register (ADCSOCFRC1) (Address Offset 1Ah) SPRUH22I – April 2012 – Revised November 2019 List of Figures Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 38 11-22. Destination Transfer Step Size Register (DST_TRANSFER_STEP) ..........11-23. Source/Destination Wrap Size Register (SRC/DST_WRAP_SIZE) ......... 11-24. Source/Destination Wrap Count Register (SCR/DST_WRAP_COUNT) List of Figures SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 39 13-7. SCI Asynchronous Communications Format ................13-8. SCI RX Signals in Communication Modes ................13-9. SCI TX Signals in Communications Mode SPRUH22I – April 2012 – Revised November 2019 List of Figures Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 40 14-31. I2C Receive FIFO Register (I2CFFRX) 1034 ................15-1. Conceptual Block Diagram of the McBSP 1039 ................... 15-2. McBSP Data Transfer Paths 1040 List of Figures SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 41 15-50. Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a Falling Edge 1094 ........... 15-51. Unexpected Frame-Synchronization Pulse With (R/X) FIG = 0 1104 SPRUH22I – April 2012 – Revised November 2019 List of Figures Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 42 1178 ..........16-17. DMA Channel Useburst Clear (DMAUSEBURSTCLR) Register 1178 ..........16-18. DMA Channel Request Mask Set (DMAREQMASKSET) Register 1179 List of Figures SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 43 17-25. EPI Clock Operation, CLKGATE = 1, WR2CYC = 0 1222 ............... 17-26. EPI Clock Operation, CLKGATE = 1, WR2CYC = 1 1223 SPRUH22I – April 2012 – Revised November 2019 List of Figures Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 44 18-3. Power Management Register (USBPOWER) in OTG A/Host Mode 1301 ........... 18-4. Power Management Register (USBPOWER) in OTG B/Device Mode 1301 List of Figures SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 45 18-52. USB Host Transmit Interval Endpoint n Register (USBTXINTERVAL[n]) 1352 ........18-53. USB Host Configure Receive Type Endpoint n Register (USBRXTYPE[n]) 1353 SPRUH22I – April 2012 – Revised November 2019 List of Figures Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 46 1407 ....... 19-27. Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6) Register 1408 ...................... 20-1. SSI Block Diagram 1411 List of Figures SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 47 21-14. UART Line Control Register (UARTLCRH) 1467 .................. 21-15. UART Control (UARTCTL) Register 1468 ............21-16. UART Interrupt FIFO Level Select (UARTIFLS) Register 1470 SPRUH22I – April 2012 – Revised November 2019 List of Figures Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 48 1509 ..............22-28. I2C Slave Interrupt Mask (I2CSIMR) Register 1509 ..............22-29. I2C Slave Raw Interrupt Status (I2CSRIS) Register 1510 List of Figures SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 49 23-46. IF3 Arbitration Register (CAN IF3ARB) [offset = 0x148] 1563 ..........23-47. IF3 Message Control Register (CAN IF3MCTL) [offset = 0x14C] 1564 SPRUH22I – April 2012 – Revised November 2019 List of Figures Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 50 25-29. Interrupt 128-133 Active Bit (ACTIVE4) Register 1625 ..............25-30. Interrupt 0-133 Priority (PRI0-PRI33) Registers 1626 ..............25-31. Software Trigger Interrupt (SWTRIG) Register 1627 List of Figures SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 51 1651 ..............25-50. MPU Region Base Address (MPUBASE) Register 1651 ............. 25-51. MPU Region Attribute and Size (MPUATTR) Register 1653 SPRUH22I – April 2012 – Revised November 2019 List of Figures Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 52 1-45. Device Configuration 10 (DC10) Register Field Descriptions ............1-46. Device Configuration 7 (DC7) Register Field Descriptions ........... 1-47. Master Subsystem Configuration (MCNF) Register Field Descriptions List of Tables SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 53 ........1-95. Control Subsystem Clock Disable (CCLKOFF) Register Field Descriptions ........1-96. M3 Configuration Write Allow (MWRALLOW) Register Field Descriptions SPRUH22I – April 2012 – Revised November 2019 List of Tables Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 54 1-142. Z1_ECSLKEY1 Register Field Descriptions ................1-143. Z2_CSMKEY0 Register Field Descriptions ................1-144. Z2_CSMKEY1 Register Field Descriptions ................1-145. Z2_CSMKEY2 Register Field Descriptions List of Tables SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 55 1-191. MTOCIPCADDR Register Field Descriptions ............... 1-192. MTOCIPCDATAW Register Field Descriptions ................ 1-193. MTOCIPCDATAR Register Field Descriptions ..............1-194. CTOMIPCBOOTSTS Register Field Descriptions SPRUH22I – April 2012 – Revised November 2019 List of Tables Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 56 4-1. GPIO Pins and Alternate Functions ................4-2. GPIO Pins and Alternate Mode Functions ..................4-3. GPIO Pad Configuration Examples List of Tables SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 57 4-51. GPIO Port A MUX 2 (GPAMUX2) Register Field Descriptions ............. 4-52. GPIO Port B MUX 1 (GPBMUX1) Register Field Descriptions SPRUH22I – April 2012 – Revised November 2019 List of Tables Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 58 Mapping of ECC bits in Read Data from ECC/Parity Address Map ..........5-4. Mapping of Parity bits in Read Data from ECC/Parity Address Map List of Tables SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 59 5-52. M0, M1 and C28T0C28_MSG_RAM Test and Initialization Register (C28RTESTINIT) Field Descriptions ........ 5-53. Lx RAM Test and Initialization Register 1 (CLxRTESTINIT1) Field Descriptions SPRUH22I – April 2012 – Revised November 2019 List of Tables Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 60 5-100. Error Position Register (ERR_POS) Field Descriptions ..........5-101. Error Status Clear Register (ERR_STATUS_CLR) Field Descriptions ............. 5-102. Error Counter Register (ERR_CNT) Field Descriptions List of Tables SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 61 ................... 6-9. M-Boot ROM Reset Cause Handling ..................6-10. M-Boot ROM Exceptions Handling .................. 6-11. M-Boot ROM Serial Boot Commands SPRUH22I – April 2012 – Revised November 2019 List of Tables Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 62 7-28. Time-Base Period High-Resolution Mirror Register (TBPRDHRM) Field Descriptions ...... 7-29. Time-Base Phase Register and Mirror Register (TBPHS / TBPHSM) Field Descriptions List of Tables SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 63 7-75. Digital Compare Filter Window Register (DCFWINDOW) Field Descriptions ..... 7-76. Digital Compare Filter Window Counter Register (DCFWINDOWCNT) Field Descriptions SPRUH22I – April 2012 – Revised November 2019 List of Tables Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 64 9-18. eQEP Interrupt Enable(QEINT) Register Field Descriptions ............9-19. eQEP Interrupt Flag (QFLG) Register Field Descriptions ............9-20. eQEP Interrupt Clear (QCLR) Register Field Descriptions List of Tables SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 65 ................11-1. Peripheral Interrupt Trigger Source Options ....................11-2. DMA Register Summary .............. 11-3. DMA Control Register (DMACTRL) Field Descriptions SPRUH22I – April 2012 – Revised November 2019 List of Tables Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 66 13-3. SCI Module Signal Summary ............... 13-4. Programming the Data Format Using SCICCR ..........13-5. Asynchronous Baud Register Values for Common SCI Bit Rates List of Tables SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 67 15-13. Selecting a Transmit Multichannel Selection Mode With the XMCM Bits 1069 ............15-14. Bits Used to Enable and Configure the Clock Stop Mode 1072 SPRUH22I – April 2012 – Revised November 2019 List of Tables Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 68 15-62. Register Bits Used to Set the Transmit Frame-Synchronization Mode 1109 ....... 15-63. How FSXM and FSGM Select the Source of Transmit Frame-Synchronization Pulses 1109 List of Tables SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 69 16-15. DMA Channel Destination Address End Pointer (DMADSTENDP) Register Field Descriptions 1172 ........16-16. DMA Channel Control Word (DMACHCTL) Register Field Descriptions 1172 SPRUH22I – April 2012 – Revised November 2019 List of Tables Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 70 17-17. EPI SDRAM Configuration (EPISDRAMCFG) Register Field Descriptions 1231 ........17-18. EPI Host-Bus 8 Configuration (EPIHB8CFG) Register Field Descriptions 1232 List of Tables SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 71 18-10. USB Transmit Interrupt Status Register (USBTXIE) Field Descriptions 1307 ..........18-11. USB Receive Interrupt Register (USBRXIE) Field Descriptions 1309 SPRUH22I – April 2012 – Revised November 2019 List of Tables Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 72 ......................Descriptions 1348 18-52. USB Control and Status Endpoint 0 High Register(USBCSRH[n]) in OTG B/Device Mode Field ......................Descriptions 1349 List of Tables SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 73 19-21. Ethernet PHY Management Register 1 – Control (MR1) Register Field Descriptions 1404 ....19-22. Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2) Register Field Descriptions 1405 SPRUH22I – April 2012 – Revised November 2019 List of Tables Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 74 21-14. UART Masked Interrupt Status (UARTMIS) Register Field Descriptions 1475 ............ 21-15. UART Interrupt Clear (UARTICR) Register Field Descriptions 1477 List of Tables SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 75 23-10. Test Register Field Descriptions 1550 ............... 23-11. Parity Error Code Register Field Descriptions 1551 ..............23-12. Auto-Bus-On Time Register Field Descriptions 1552 SPRUH22I – April 2012 – Revised November 2019 List of Tables Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 76 25-13. Interrupt 64-95 Set Enable 2 (EN2) Register Field Descriptions 1612 ..........25-14. Interrupt 96-127 Set Enable 3 (EN3) Register Field Descriptions 1613 List of Tables SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 77 25-57. MPU Region Base Address (MPUBASE) Register Field Descriptions 1652 ................... 25-58. Example SIZE Field Values 1652 ..........25-59. MPU Region Attribute and Size (MPUATTR) Field Descriptions 1653 SPRUH22I – April 2012 – Revised November 2019 List of Tables Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 78: Preface
For a complete listing of related documentation and development-support tools for these devices, visit the Texas Instruments website at http://www.ti.com. Additionally, the TMS320C28x CPU and Instruction Set Reference Guide (SPRU430) and TMS320C28x Floating Point Unit and Instruction Set Reference Guide (SPRUEO2) must be used in conjunction with this TRM.
Page 79: System Control And Interrupts
Code Security Module (CSM) ....................1.11 µCRC Module ............... 1.12 Inter Processor Communications (IPC) .................. 1.13 System Control Registers SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 80: Signal Description
VDD18. Pull low to enable the VREG18EN manual for pin Fixed Fixed Fixed internal 1.8-V voltage regulator (VREG18), pull high to disable VREG18. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 81: System Control Functional Description
The master subsystem device identification registers are: DID0 and DID1. The control subsystem device identification registers are: PARTID and REVID. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 82: Device Configuration Registers
Table 1-3 shows various reset signals in this device and how it affects different hardware modules in the device. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 83: Device Level Reset Sources
Please refer to the Boot ROM chapter for more details. Table 1-4 provides information for the device bring up time-line on power-up. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 84: Device Bring-Up Time Line
It is recommended to connect both XRS and ARS pins together externally using a single trace. The internal reset which can pull ARS low is caused by the power-on reset (POR). System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 85 ROM. Refer to the Boot ROM chapter for more details on how boot ROM handles this reset. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 86 ACIBRESET bit (bit 30) of the DEVICECNF register. Refer to the DEVICECNF register for details. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 87 SRXRST. SRXRST is triggered by a master software reset or by a master debugger reset. SRXRST is also triggered by an XRS. Figure 1-1 shows reset connectivity on the device. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 88: Resets Connectivity
C28x CLBISTRST SUBSYSTEM ‘0’ C28RSTIN C28SYSRST C28x SYNC DEGLITCH M3SSCLK C28x WDOG RESET INPUT SIGNAL STATUS C28NMIWD DEVICECNF REG System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 89: Handling Of Resets At System Level
Same as WDT1 reset above Same as MNMIWD above Master SRXRST, Software C28RSTIN reset Master SRXRST, Debugger C28RSTIN Reset SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 90 XRS reset, then boot ROM should not set clock dividers to default (for example, a debugger reset by the user while developing code on bench). System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 91 MRESC register which tells which C28NMI was unserviced that caused a reset. Unlike the master subsystem which has a reset cause register, the control subsystem does not. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 92: Wir Mode
EMU0 and EMU1 pins can put the device in WIR mode. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 93: Entering Wir Mode
Figure 1-2 shows how each boot ROM puts respective CPU in WIR mode. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 94: Exiting Wir Mode
The user can then directly write a value other than the WIR_MODE_YES value (refer to Table 1-7) to these bits, and not set the sample bit. Therefore, when System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 95: Exceptions And Interrupts Control
IPC. This has to be taken care of by the user as per the application requirements. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 96: Master Subsystem Exceptions Handling
For bus errors during fetches, even if the M3 sees an error response, it will not internally bus fault System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 97: Master Subsystem Non-Maskable Interrupt (Mnmi) Module
NMI to the Cortex-M3 on the master subsystem and the registers associated with them. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 98: Master Subsystem Nmi Sources And Mnmiwd
The MNMIWD counter will stop counting and reset back to zero once all the set MNMIFLG bits and the NMIINT flag bit in the MNMIFLG register are cleared. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 99 "0"), if the error condition that triggers this NMI occurs, the ACIBERR bit is set in the MNMIFLG register. This error is generated if a stuck condition is detected on the ACIB INTS or READY signals. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 100: Control Subsystem Pie
(INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 101: Pie Interrupts Multiplexing
INTx.2 INTx.3 From INTx.4 INTx Peripherals or INTx.5 External INTx.6 Interrupts INTx.7 INTx.8 PIEACKx (Enable) (Flag) (Enable/Flag) PIEIERx(8:1) PIEIFRx(8:1) SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 102 CPU interrupt enable (IER) register or the debug interrupt enable register (DBGIER) and the global interrupt mask (INTM) bit. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 103: Cpu Level Interrupt Handling
In this special case, the DBGIER is used and the INTM bit is ignored. If the DSP is in real-time mode and the CPU is running, the standard interrupt-handling process applies. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 104: Enabling Interrupt
M0 and M1 memory blocks are treated as SARAM blocks and can be used freely without any restrictions. After a device reset operation, the vector table is mapped as shown in Table 1-11. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 105: Control Subsystem C28X Processor After Reset Flow
C28x Mode 24x/240xA Source-Compatible C27x Object-Compatible 0 (Default at reset) The reset vector is always fetched from the boot ROM. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 106: Pie Interrupt Sources And External Interrupts Xint1/Xint2/Xint3
PIE module also uses the PIEIER and PIEIFR registers to decode to which interrupt service routine the CPU should branch. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 107 CPU IFR register, the following procedure should be followed: 1. Disable global interrupts (INTM = 1). 2. Set the EALLOW bit. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 108: Multiplexed Interrupt Request Flow
The proper enable bit must be set (PIEIERx.y = 1) and b. The PIEACKx bit for the group must be clear. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 109 No peripheral interrupts are assigned to the group. For example, PIE group 11 and 12 do not have any peripherals attached to them. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 110: Pie Vector Table Mapping
Reset is always fetched from location 0x003F FFC0 in Boot ROM. All the locations within the PIE vector table are EALLOW protected. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 111 Reserved INT1.4 0x0000 0D46 XINT1 INT1.5 0x0000 0D48 XINT2 INT1.6 0x0000 0D4A Reserved TINT0 (C28x Timer INT1.7 0x0000 0D4C SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 112 1 (highest) SPITXINTA (SPI- INT6.2 0x0000 0D92 INT6.3 0x0000 0D94 Reserved INT6.4 0x0000 0D96 Reserved MRINTA (McBSP- INT6.5 0x0000 0D98 System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 113 8 (lowest) PIE Group 11 Vectors -MUXed into CPU INT11 INT11.1 0x0000 0DE0 MTOCIPCINT1 1 (highest) INT11.2 0x0000 0DE2 MTOCIPCINT2 SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 114 The following events also clear an IFR flag: • The CPU acknowledges the interrupt. • The 28x device is reset. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 115 For XINT1/XINT2/XINT3, there is also a 16-bit counter that is reset to 0x000 whenever an interrupt edge is detected. These counters can be used to accurately time stamp an occurrence of the interrupt. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 116: Control Subsystem Exceptions Handling
Figure 1-9 explains how an NMI is generated to the control subsystem CPU. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 117: Control Subsystem Nmi Sources And Cnmiwd
Control Subsystem NMI Sources This section explains the error events that can generate an NMI to the control subsystem CPU. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 118 Real-Time Run-Free Mode When the CPU is in real-time run-free mode, the NMI watchdog counter operates as normal. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 119: Safety Features
After modifying registers, they can once again be protected by executing the EDI instruction to clear the EALLOW bit. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 120: Missing Clock Detection Logic
ISR for the NMI. If the CNMIWD expires it will generate a reset to the C28 CPU and C28 subsystem. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 121: Reference Clock Limits For Detecting A Missing Clock
Ref Clock Frequency REFCLKLOLIMIT REFCLKHILIMIT 4 MHz (250ns) 10 MHz (100ns) 20 MHz (50ns) 0x11 100 MHz (10ns) 0x4E 0x52 SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 122: Missing Clock Detection Logic
4. C28 side PWMs tripped based on low limit configuration 1. Generate NMI to M3 and C28 CPU 2. Start both NMIWD counters System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 123: Pllslip Detection
In the event of a mismatch during a C28 NMI vector fetch, an NMI is generated to the M3 CPU. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 124: Nmiwds
If the error counter reaches a predefined user configured limit then an interrupt is generated to each CPU. Refer to the Internal Memory chapter for more details on RAM errors. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 125: Ecc Enabled Flash Memory
Internal Memory chapter for more details on shared resources. Refer to the clocking diagrams in the master and control subsystems for more details on these clock sources. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 126: Clock Sources
PLL is OSCCLK and USBPLL is OSCCLK or GPIO_XCLKIN. Both the PLLs are powered down in the deep sleep mode. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 128: Master Subsystem Clocks And Low Power Mode Configuration
USBPLL and CAN modules have the option to choose a clock source other than OSCCLK as shown in Figure 1-11. Refer to the respective sections for more details on USB and CAN clocking configurations. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 130: Control Subsystem Clocking
Figure 1-12 shows the clocking control on the control subsystem. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 131: Control Subsystem Clocks And Low Power Mode Configuration
Refer to Section 1.9 for more details on these registers. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 132 PCLKCR3 registers. These registers are accessible only by the C28 CPU and are similar to earlier C2000 family of devices. Figure 1-13 shows various clock domain on the control subsystem. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 133: Control Subsystem Peripherals Clocking
If this is done, the current drawn will be more than required. To avoid this, only enable the clocks required by the application. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 134: Clocking Control Semaphore Functionality
It also cannot set the SEM bits to "0,1". Only the master System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 135: Acib And Analog Peripherals Clocking
1-12. Note that only the master subsystem can configure the XCLKOUT divider. The clock output on this GPIO pin is the output of PLLSYSCLK divided by the SYSDIVSEL divider. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 136: 32-Bit Cpu Timers 0/1/2
The timer registers are connected to the Memory Bus of the C28x processor. The timing of the CPU timers are synchronized to SYSCLKOUT of the processor clock. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 137: Timerxtim Register (X = 0, 1, 2)
Figure 1-17. TIMERxTIMH Register (x = 0, 1, 2) TIMH R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 138: Timerxprd Register (X = 0, 1, 2)
This flag gets set when the CPU-timer decrements to zero. Writing a 1 to this bit clears the flag. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 139: Timerxtpr Register (X = 0, 1, 2)
PSCH:PSC, and the TIMH:TIM decrements by one. TDDRH:TDDR also reloads the PSCH:PSC whenever the timer reload bit (TRB) is set by software. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 140: Low Power Modes
Master Subsystem Low-Power Modes Configuration The master subsystem has the following low-power modes: • Sleep mode • Deep-sleep mode System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 141: M3 Subsystem Low-Power Modes
1.9.1.1.1.5). When the processor executes a WFI instruction, it stops executing instructions and enters sleep mode. See the Cortex™-M3 Instruction Set Technical User's Manual for more information. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 142 M3 power modes, please refer to the Power Management Chapter of the Cortex™-M3 Technical Reference Manual. 1.9.1.2 Control Subsystem Low-Power Modes Configuration Table 1-26 summarizes the various low-power modes. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 143: Low-Power Modes Configuration
QUALSTDBY bits (bits [7:2] of the CLPMCR0 register) . Refer to the GPIOs chapter for more details on the GPIOLPMSELx registers. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 144: Code Security Module (Csm)
Each zone has its own 128 bit CSM password. The zone can be unsecured by executing the password match flow (PMF). Table 1-28 shows the levels of security. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 145: Security Levels
NOTE: Access to the secure memory from the debuuger does not trip the debug probe. These accesses are just blocked and return ‘0’. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 146 EXEONLY feature on flash sector A, which contains all of the security settings, for complete security initialization. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 147: Csm Impact On Other On-Chip Resources
Register Name Reset Values Register Description 0x20-0000 Z1_CSMPSWD0 User Defined Low word (32-bit) of the 128-bit CSM password for zone1 SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 148: M3 Zone2 - Reserved Locations In Flash Memory
High word (32-bit) of the 128- bit CSM password 0x13-FFF4 ECSLPSWD0 User Defined Low word (32-bit) of the 64-bit CSM password System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 149 (PWL) followed by eight 16-bit (or four 32-bit) writes to CSMKEY registers. Figure 1-23 shows how PMF helps to initialize the security logic registers and disable security logic. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 150: Csm Password Match Flow
Are CSM PWL = All Write the CSM Password of that zone into CSMKEY(0/1/2/3) registers Correct Password? Zone Unsecure System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 151 *CSM++ = 0x44443333; // Register CSMKEY1 at 0xAE2 *CSM++ = 0x66665555; // Register CSMKEY2 at 0xAE4 *CSM++ = 0x88887777; // Register CSMKEY3 at 0xAE6 SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 152: Zone Security Status
(PWL) followed by eight writes to KEY registers. Figure 1-24 shows how the PMF helps to initialize the security logic registers and disable security logic. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 153: Ecsl Password Match Flow
Are ECSL PWL = All Write the ECSL Password of that zone into ECSLKEYx registers Correct Password? Zone ECSL Unlock SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 154 *ECSL++ = 0x44443333; // Register ECSLKEY1 at 0xAF2 Table 1-34 shows different conditions for any zone's ECSL to be secure or non-secure. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 155: Do's And Don'ts To Protect Security Logic
CRC result for that perticual read. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 156: Crc Polynomials
Refer to the Boot ROM chapter for more information on these IPC boot registers. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 157: Msgrams
Message RAMs to build a software handshake mechanism between the two cores. Figure 1-25 shows the IPC flag messaging and interrupt mechanism. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 158: Mtocipc Communication
CLR register on the M3 and the ACK register on the C28x. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 159: Ctomipc Communication
(CTOMIPCINT1 to CTOMIPCINT4) to the M3 PIE if enabled. The remaining 28 bits (bit 4 to bit 31) can be used as explained above in a software-based handshake (flag/ack) mechanism. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 160: Examples For Software Ipc Procedure
IPC Message registers that the master subsystem can use to convey a message to the control subsystem are given in Table 1-36. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 161: Flash Pump Semaphore
M3 core cannot erase/program the M3 flash bank, but the M3 core can execute code and/or read data from the M3 flash bank. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 162: Clock Configuration Semaphore
(a 2-bit field called SEM in CLKREQUEST registers). System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 163: Mastership Of Clock Configuration Registers For Different States Of Clock Configuration Semaphore
8. Put the PLL back into the clock path 9. Modify the clock dividers as desired by the application SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 164: Free Running Counter
If either core is executing, the counter runs. It is suggested that the user application should disable interrupts when reading the counters. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 165: System Control Registers
GPIOHBCTL Performance Bus 0x6C MWRALLOW M3SYSRST Control Register Run Mode Clock RCGC0 Gating Control 0x100 MWRALLOW M3SYSRST Register 0 SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 166 MWRALLOW M3SYSRST Period Register 0x400F:B9 M3 MWRALLOW Configuration Registers: M3SYSRST M3 Configuration MWRALLOW Privelege Mode M3SYSRST Write Allow Register System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 167 SYSPLLSTS 0x08 Status Register System Clock Divider SYSDIVSEL 0x0C EALLOW MWRALLOW Register Control Subsystem Device 0x400F:B9 0x0886 Configuration Registers: SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 168 PCLKCR3 0X20 EALLOW C28SYSRST Control Register 3 C28 Wait-In-Reset CWIR 0X2B EALLOW Register Control Subsystem NMI 0x7060 Configuration Registers: System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 169 Zone1 Grab RAM-blocks Z1_GRABRAM Register for M3 0x94 M3SYSRST Zone1 Grab Flash-Sectors Z2_GRABSEC Register for M3 0x98 M3SYSRST Zone2 SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 170 C28 to M3 IPC C28SYSRST, CTOMIPCCOM 0x10 0x20 Command Register SRXRST CTOMIPCADD C28 to M3 IPC C28SYSRST, 0x12 0x24 Address Register SRXRST System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 171 C28 to M3 IPC Data 0x16 0x2C SRXRST Read Register C28x M3 to C28 IPC MTOCIPCCOM 0x18 0x30 SRXRST Command Register C28x SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 172 EALLOW MWRALLOW SRXRST request register Clock configuration CCLKREQUES semaphore C28 0x26 EALLOW MWRALLOW SRXRST request register Reserved Reserved 0x28 System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 173: Device Identification And Device Configuration
144 pins 12-8 Reserved Reserved TEMP Temperature Range Extended Industrial Temperature Range (-40°C to 105°C). PACKAGE Package Type LQFP SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 174: Device Configuration 1 (Dc1) Register
WDT0 is present Reserved Reserved JTAG JTAG Debugger Interface JTAG debugger interface is not present JTAG debugger interface is present System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 175: Device Configuration 2 (Dc2) Register
II2C0 Whether I2C0 is present or not depends on the device configuration. I2C0 is not present I2C0 is present SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 176 UART0 Whether UART0 is present or not depends on the device configuration. UART0 is not present UART0 is present. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 177: Device Configuration 4 (Dc4) Register
Whether GPIOG is present or not depends on the device configuration. GPIO PortG is not present GPIO PortG is present SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 178 Whether GPIOA is present or not depends on the device configuration. GPIO PortA is not present GPIO PortA is present System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 179: Device Configuration 6 (Dc6) Register
Whether CAN0 is present or not depends on the device configuration. CAN0 is not present CAN0 is present 23-1 Reserved Reserved SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 180: Device Configuration 7 (Dc7) Register
Reserved µCRC µCRC Configuration µCRC is disabled µCRC is present Reserved Reserved FLASH M3 Flash Size Configuration 512KB 256KB System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 181: Serial Port Loop Back Control (Serploop) Register
Reading this bit gives the power state of the Analog Subsystem. Analog subsystem power not present Analog subsystem power present SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 182: C28 Device Part Id (Partid) Register
Field Value Description 15-0 REVID Silicon Revision Number These 16-bits specify the silicon revision number for the particular part. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 183: Control Subsystem Device Configuration (Devicecnf) Register
R-0:0 Reserved Reserved HRPWM R-0:0 R-0:0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 184: Control Subsystem Peripheral Configuration 1 (Ccnf1) Register
Configuration When set, this enables the respective eCAP module. Respective eCAP module is disabled Respective eCAP module is enabled System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 185: Control Subsystem Peripheral Configuration 2 (Ccnf2) Register
Reserved EPWM9 ePWM9 Configuration. When set, this enables the ePWM9 module. ePWM9 module is disabled ePWM9 module is enabled SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 186: Control Subsystem Peripheral Configuration 3 (Ccnf3) Register
When set, this enables the C28 DMA module. C28 DMA module is disabled C28DMA module is enabled 10-0 Reserved Reserved System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 187: Control Subsystem Peripheral Configuration 4 (Ccnf4) Register
Reserved Reserved S7-0 S7-0 Shared Memory Configuration S7-0 Shared RAM configuration. S7-0 RAM is disabled S7-0 RAM is enabled SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 188: Reset Control And Status Registers
Note: This flag is 2 bits to take care of any error conditions that may cause inadvertent setting of a single bit flag; System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 189 15-1 Reserved Reserved CRES C28 Reset Status Bit C28 CPU is in reset C28 CPU is out of reset SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 190: Master Reset Cause (Mresc) Register
If set to 11, indicates that M3 CPU HWBIST has run to completion and issued a reset to the M3 CPU. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 191: C28 Reset Cause Register (Cresc) Register
If ‘0’ then there was no C28 NMI WDOG reset since the previous POR Clears this bit. No effect SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 192: Software Reset Control 0 (Srcr0) Register
When this bit is set, Watchdog Timer module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. Reserved Reserved System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 193: Software Reset Control 1 (Srcr1) Register
When this bit is set, SSI3 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 194: Software Reset Control 2 (Srcr2) Register
When this bit is set, EMAC is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 27-17 Reserved Reserved System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 195: Software Reset Control 3 (Srcr3) Register
R/W-0 R/W-0 R-0:0 Reserved UART4 R-0:0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 196: Software Reset Control 3 (Srcr3) Register Field Descriptions
When this bit is set, UART4 module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 197: Wirmode Registers
Reading this bit will give the state of the EMU1 pin on reset or when sampled. Has no effect Forces the bit to "1" SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 198: Exception And Interrupts
This bit is always set to '1', meaning any NMI condition will generate an NMI interrupt to the M3 CPU and kick off the NMI watchdog counter. The bit cannot be cleared by the user. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 199: M3Nmi Flag (Mnmiflg) Register
NMIFLGCLR register or by an XRS reset. No CLOCKFAIL condition pending CLOCKFAIL condition generated SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 200: M3Nmi Flag Clear (Mnmiflgclr) Register
Note 2: Users should clear the pending FAIL flag first and then clear the NMIINT flag. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 201: M3Nmi Flag Force (Mnmiflgfrc) Register
Writing a 1 to these bits will set the respective FAIL flag in the NMIFLG and NMISHDFLG registers. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 202: M3Nmi Watchdog Counter (Mnmiwdcnt) Register
Writing a PERIOD value that is smaller then the current counter value will automatically force an NMIRS to the M3 and hence reset the watchdog counter. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 203: C28 Nmi Configuration (Cnmicfg) Register
C28RAMUNCERR CLOCKFAIL NMIINT R-0:0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 204: C28 Nmi Flag (Cnmiflg) Register Field Descriptions
NOTE: If hardware is trying to set a bit to "1" while software is trying to clear a bit to "0" on the same cycle, hardware has priority. Users should clear the pending FAIL flag first and then clear the NMIINT flag. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 205: C28 Nmi Flag Clear (Cnmiflgclr) Register
NMIINT NMI Interrupt Flag Clear Ignored; always reads back 0. Clears the corresponding flag bit in the NMIFLG register. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 206: C28 Nmi Flag Force (Cnmiflgfrc) Register
If no enabled "NMI" flag is set, then the counter will reset to zero and remain at zero until an enabled "NMI" flag is set. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 207: C28 Nmi Watchdog Period (Cnmiwdprd) Register
Reserved PIEACK R/W1C-1 LEGEND: R/W1C = Read/Write 1 to clear; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 208: Pie, Intx Group Enable Register (Pieierx) (X = 1 To 12)
NOTE: Care must be taken when clearing PIEIER bits during normal operation. See Section Section 1.5.4.3.2 for the proper procedure for handling these bits. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 209: Pie, Intx Group Flag Register (Pieifrx) (X = 1 To 12)
The following events also clear an IFR flag: • The CPU acknowledges the interrupt. • The 28x device is reset. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 210: Cpu Interrupt Flag Register (Ifr)
At least one INT6 interrupt is pending. Write a 0 to this bit to clear it to 0 and clear the interrupt request System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 211 When using the OR IER and AND IER instructions to modify IER bits make sure they do not modify the state of bit 15 (RTOSINT) unless a real-time operating system is present. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 212: Cpu Interrupt Enable Register (Ier)
Interrupt 7 enable. INT7 enables or disables CPU interrupt level INT7. Level INT7 is disabled Level INT7 is enabled System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 213: Debug Interrupt Enable Register (Dbgier)
Data logging interrupt enable. DLOGINT enables or disables the CPU data logging interrupt Level INT6 is disabled Level INT6 is enabled SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 214 INT1 Interrupt 1 enable.INT1 enables or disables CPU interrupt level INT1. Level INT1 is disabled Level INT1 is enabled System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 215: C28 External Interrupt 1 Configuration Register (Xint1Cr)
Reserved POLARITY Rsvd ENABLE R/W-0:0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 216: C28 External Interrupt 1 Counter Register (Xint1Ctr)
The counter is a read only register and can only be reset to zero by a valid interrupt edge or by the C28 SYSRSN reset. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 217: C28 External Interrupt 3 Counter Register (Xint3Ctr)
System PLL is powered off; clock to the system is a direct feed from X1. System PLL is enabled and clock to the system will depend on SYSPLLMULT and SYSPLLCLKEN register bit configuration. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 218: Safety Control Registers
Figure 1-86. M3 Configuration Lock (MLOCK) Register Reserved MSxMSELLOCK R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 219: Missing Clock Status (Mclksts) Register
R-0:0 R/W-0 Reserved REFCLKOFF R-0:0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 220: Missing Clock Enable (Mclken) Register
Reserved R-0:0 REFCLKHILIMIT REFCLKLOLIMIT R/W-0x7A R/W-0x2 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 221: C28 User_Swreg1 Register
Table 1-103. C28_USER_SWREG2 Register Field Descriptions Field Value Description Reserved Reserved 14-9 SWREG2 General purpose register for C28 software use. Reserved Reserved SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 222: Clocking Control Registers
Reserved R-0x1 Reserved SYSDIVSEL R-0:0 R/W-11 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 223: System Pll Lock Status (Syspllsts) Register
Figure 1-96. Master Subsystem Clock Divider (M3SSDIVSEL) Register Reserved M3SSDIVSEL R-0:0 R/W-10 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 224: Xpll Clkout Control (Xpllclkcfg) Register
UPLLCLKEN UPLLEN R-0:0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 225: Usb Pll Multiplier (Upllmult) Register
USB PLL Fractional Multiplier Fractional multiplier = 0 Fractional multiplier = 0.25 Fractional multiplier = 0.5 Fractional multiplier = 0.75 Reserved Reserved SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 226: Usb Pll Lock Status (Upllsts) Register
Bit Clock Source Select CAN0 bit clock = M3 SS_CLK CAN0 bit clock = OSCCLK CAN0 bit clock = GPIO_XCLKIN System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 227: Bit Clock Source Selection For Can1 (Can1Bclksel) Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 228: Run Mode Clock Gating Control Register 0 (Rcgc0)
Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the module generates bus faults. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 229: Sleep Mode Clock Gating Control Register 0 (Scgc0)
Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the module generates bus faults. Reserved Reserved SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 230: Run Mode Clock Gating Control Register 1 (Rcgc1)
Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the module generates bus faults. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 231: Sleep Mode Clock Gating Control Register 1 (Scgc1)
Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the module generates bus faults. 29-20 Reserved Reserved SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 232 Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the module generates bus faults. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 233: Deep Sleep Mode Clock Gating Control Register 1 (Dcgc1)
Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the module generates bus faults. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 234: Run Mode Clock Gating Control Register 2 (Rcgc2)
Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the module generates bus faults. 27-17 Reserved Reserved System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 235 Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the module generates bus faults. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 236: Sleep Mode Clock Gating Control Register 2 (Scgc2)
Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the module generates bus faults. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 237 Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the module generates bus faults. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 238: Deep Sleep Mode Clock Gating Control Register 2 (Dcgc2)
Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the module generates bus faults. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 239: Run Mode Clock Gating Control Register 3 (Rcgc3)
R/W-0 R-0:0 Reserved UART4 R-0:0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 240: Deep Sleep Mode Clock Gating Control Register 3 (Dcgc3)
1.13.7.25 Deep Sleep Clock Configuration (DSLPCLKCFG) Register NOTE: M3 Watchdog 1 will be clocked by the deep sleep clock selected by the DSLPCLKCFG.DSOSCSRC bits. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 241: Deep Sleep Clock Configuration (Dslpclkcfg) Register
Use the 32-kHz clock as the clock source Use the 10-MHz ATOB clock as the clock source 0x3-0x7 Reserved Reserved Reserved SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 242: C28 Cpu Timer 2 Clock Configuration (Clkctl) Register
HRPWMENCLK R-0:0 R/W-0 R-0:0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 243: Peripheral Clock Control Register 1 (Pclkcr1)
(n = 6-1) When set, this enables the clock to the respective eCAP module. Clock is disabled Clock is enabled SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 244: Peripheral Clock Control Register 2 (Pclkcr2)
Clock Enable When set, this enables the clock to the ePWM9 module. ePWM9 clock is disabled ePWM9 clock is enabled System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 245: Peripheral Clock Control Register 3 (Pclkcr3)
When set, this enables the clock to the CPU timers on the C28 subsystem. (n = 2-0) Timer clock is disabled Timer clock is enabled Reserved Reserved SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 246: High-Speed Clock Prescaler (Chispcp) Register
LSPCLK = SYSCLKOUT / 8 LSPCLK = SYSCLKOUT / 10 LSPCLK = SYSCLKOUT / 12 LSPCLK = SYSCLKOUT / 14 System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 247: C28 Xclkout Divider Register (Cxclk)
SYSCLKOUT. The ratios are given below. XCLKOUT = C28 SYSCLKOUT/4 XCLKOUT = C28 SYSCLKOUT/2 XCLKOUT = C28 SYSCLKOUT XCLKOUT = Off SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 248: Master Subsystem Code Security Module (Csm) Registers
Figure 1-129. Z1_CSMKEY3 Register CSMKEY R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 249: Z1_Ecslkey0 Register
Value Description 31-0 CSMKEY To unlock M3 zone2, write the same value in CSMPSWD0 of zone2 to this register. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 250: Z2_Csmkey1 Register
Figure 1-136. Z2_ECSLKEY0 Register ECSLKEY R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 251: Z2_Ecslkey1 Register
Dummy read to M3-Zone1 CSM PWL (Password locations) have not been performed. Dummy read to M3-Zone1 CSM PWL (Password locations) have been performed. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 252: Z2_Csmcr Register
R=0/W=1 CSM-ALLONE ECSL- CSM-ALLZERO Reserved ALLZERO LEGEND: R/W = Read/Write; R = Read only; -n = value after reset System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 253: Z2_Csmcr Register Field Descriptions
CSM Passwords of M3 Zone2 does not contain all 0's CSM Passwords of M3 Zone2 contains all 0's Reserved Reserved SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 254: Z1_Grabsectr Register
Request to allocate M3 Flash Sector F to M3 Zone1 Request to allocate M3 Flash Sector F to M3. Zone1 Request to make M3 Flash Sector F Non-Secure System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 255 Request to allocate M3 Flash Sector M to M3 Zone1 Request to allocate M3 Flash Sector M to M3 Zone1 Request to make M3 Flash Sector M Non-Secure SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 256: Z1_Grabramr Register
GRABSECTL GRABSECTM R-00 R-00 R-00 R-00 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 257: Z2_Grabsectr Register
Request to allocate M3 Flash Sector I to M3 Zone2 Request to allocate M3 Flash Sector I to M3 Zone2 Request to make M3 Flash Sector I Non-Secure SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 258: Z2_Grabramr Register
Request to allocate M3 C1 RAM to M3 Zone2 Request to allocate M3 C1 RAM to M3 Zone2 Request to make M3 C1 RAM Non-Secure System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 259 Request to allocate M3 C0 RAM to M3 Zone2 Request to allocate M3 C0 RAM to M3 Zone2 Request to make M3 C0 RAM Non-Secure SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 260: Z1_Exeonlyr Register
Execute only select register sector J Execute-only is enabled for Sector J on Zone 1 Execute-only disabled for Sector J on Zone 1 System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 261: Z2_Exeonlyr Register
Execute only select register Sector E Execute-only is enabled for Sector E on Zone 2 Execute-only is disabled for Sector E on Zone 2 SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 262: Otpseclock Register
µCRC does not have ability to calculate CRC on secured memories (including EXE-Only flash sectors). µCRC has the ability to calculate CRC on M3 secured memories (including EXE-Only flash sectors) System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 263 JTAG Port is enabled. Debugger (for example, CCS) can be connected to the Cortex-M3 as well as the C28x. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 264: Control Subsystem Code Security Module (Csm) Registers
Figure 1-150. CSMKEY3 Register CSMKEY R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 265: Csmcr Register
Dummy read to control subsystem CSM PWL (Password locations) have not been performed. Dummy read to control subsystem CSM PWL (Password locations) have been performed. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 266: Ecslkey0 Register
To disable ECSL logic active on the control subsystem, the user needs to write the same value in ECSLPSWD1 of zone1 to this register. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 267: Exeonlyr Register
Execute-Only protection is disabled for C28x Flash Sector F (only if it is allocated to the control subsystem) SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 268: Μcrc Register Description
Table 1-166. µCRC Register Summary Name Address (Offset) Size (X32) Description µCRCCONFIG µCRC Configuration Register µCRCCONTROL µCRC Control Register System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 269: Μcrcconfig Register
Figure 1-157. µCRCRES Register RESULT R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 270: Master Subsystem Ipc Registers
MTOCIPCFLG is set. The status of this bit is not readable in this register – it is readable in the MTOCIPCFLG and STS registers. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 271 MTOCINT1 is raised to the C28 PIE. The status of this bit is not readable in this register – it is readable in the corresponding bit in the MTOCIPCFLG and STS registers. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 272: M3 To C28 Ipc Clear (Mtocipcclr) Register
MTOCIPCFLG is cleared. The status of this bit is not readable in this register – it is readable in the MTOCIPCFLG and STS registers. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 273 MTOCIPCFLG is cleared. The status of this bit is not readable in this register – it is readable in the MTOCIPCFLG and STS registers. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 274: M3 To C28 Core Flag (Mtocipcflg) Register
MTOCIPCSET bit has been written with a ‘1’ and MTOCIPCCLR or MTOCIPCACK bit has not been written with a ‘1." System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 275 MTOCIPCSET bit has been written with a ‘1’ and MTOCIPCCLR or MTOCIPCACK bit has not been written with a ‘1." SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 276: M3 To C28 Core Ipc Acknowledge (Ctomipcack) Register
CTOMIPCFLG and CTOMIPCSTS to ‘0’. The status of this bit is not readable in this register – it is readable in the CTOMIPCFLG and STS registers. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 277 CTOMIPCFLG and CTOMIPCSTS to ‘0’. The status of this bit is not readable in this register – it is readable in the CTOMIPCFLG and STS registers. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 278: C28 To M3 Core Ipc Status (Ctomipcsts) Register
CTOMIPCSET bit has been written with a ‘1’ and CTOMIPCCLR or CTOMIPCACK bit has not been written with a ‘1." System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 279 CTOMIPCSET bit has been written with a ‘1’ and CTOMIPCCLR or CTOMIPCACK bit has not been written with a ‘1." SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 280: M3 Flash Semaphore Register
• State transitions from "00" → "11" and "11" → "00" are allowed by design. However these transitions will not result in change in ownership. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 281: Control Subsystem Ipc Registers
IPC6 IPC5 IPC4 IPC3 IPC2 IPC1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 282: Ctomipcset Register Field Descriptions
CTOMIPCFLG is set. The status of this bit is not readable in this register – it is readable in the CTOMIPCFLG and STS registers. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 283 IPC6 IPC5 IPC4 IPC3 IPC2 IPC1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 284: Ctomipcclr Register
CTOMIPCFLG is cleared. The status of this bit is not readable in this register – it is readable in the CTOMIPCFLG and STS registers. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 285 IPC6 IPC5 IPC4 IPC3 IPC2 IPC1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 286: Ctomipcflg Register
CTOMIPCSET bit has been written with a ‘1’ and CTOMIPCCLR or CTOMIPCACK bit has not been written with a ‘1’. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 287 IPC6 IPC5 IPC4 IPC3 IPC2 IPC1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 288: Mtocipcack Register
MTOCIPCFLG and MTOCIPCSTS to ‘0’. The status of this bit is not readable in this register – it is readable in the MTOCIPCFLG and STS registers. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 289 IPC6 IPC5 IPC4 IPC3 IPC2 IPC1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 290: Mtocipcsts Register
MTOCIPCSET bit has been written with a ‘1’ and MTOCIPCCLR or MTOCIPCACK bit has not been written with a ‘1’. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 291: C28 Flash Semaphore Register
Writing the value 0x4CE7395 will allow writes to the SEM bits or writes are ignored. Reads will return 0. Note: This is to prevent spurious writes to the semaphore bits. Reserved Reserved SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 292: C28 Clock Semaphore Register
• State transitions from "00" → "11" and "11" → "00" are allowed by design. However these transitions will not result in change in ownership. System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 293: Master And Control Subsystem Ipc Registers
IPC commands from the C28 to the M3 CPU. It is read/write for the C28 CPU and read only for the M3 CPU. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 294: Ctomipcaddr Register
Figure 1-178. MTOCIPCCOM Register COMMAND R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 295: Mtocipccom Register Field Descriptions
IPC commands from the M3 to the C28 CPU. It is read/write to the M3 CPU and read only to the C28 CPU. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 296: Mtocipcaddr Register
Figure 1-182. CTOMIPCBOOTSTS Register BOOTSTS R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset System Control and Interrupts SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 297: Mtocipcbootmoderegister
C28 boot mode to enter. It is read/write to the M3 CPU and read only to the C28 CPU. SPRUH22I – April 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 298: M3 General-Purpose Timers
Page ....................GPTM Features ....................Block Diagram ..................Functional Description ................Initialization and Configuration ....................Register Map ..................Register Descriptions M3 General-Purpose Timers SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 299: Gptm Features
Detect Odd CCPPin GPTMTBMR TB Comparator GPTMTBILR GPTMTBMATCHR Timer B Free-Running GPTMTBPR Value GPTMTBPMR 0x0000 (DownCounterModes) 0xFFFF (UpCounterModes) System Clock SPRUH22I – April 2012 – Revised November 2019 M3 General-Purpose Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 300: Functional Description
(GPTMTAV) register and the GPTM Timer B Value (GPTMTBV) register. The prescale counters are initialized to 0x00: the GPTM Timer A Prescale (GPTMTAPR) register, and the GPTM Timer B Prescale (GPTMTBPR) register . M3 General-Purpose Timers SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 301: Timer Modes
Table 2-3. 16-Bit Timer With Prescaler Configurations Prescale #Clock (Tc) Max Time Units 00000000 0.6554 00000001 1.3107 00000010 1.9661 ------------ SPRUH22I – April 2012 – Revised November 2019 M3 General-Purpose Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 302: Timer Daisy Chain
If the TASTALL and/or TBSTALL bits in the GPTMCTL register are set, the timer does not freeze if the RTCEN bit is set in GPTMCTL. M3 General-Purpose Timers SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 303: Edge-Count Mode Example
Figure 2-3. Edge-Count Mode Example Timer stops, Timer reload flags on nextcycle Ignored Ignored Count asserted 0x000A 0x0009 0x0008 0x0007 0x0006 Input Signal SPRUH22I – April 2012 – Revised November 2019 M3 General-Purpose Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 304: 16-Bit Input Edge-Time Mode Example
GPTMTnR=X GPTMTnR=Y GPTMTnR=Z 0xFFFF Time Input Signal 2.3.2.5 PWM Mode NOTE: The prescaler is not available in 16-Bit PWM mode. M3 General-Purpose Timers SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 305: Dma Operation
No other special steps are needed to enable Timers for µDMA operation. Refer to the Micro Direct Memory Access (µDMA) chapter for more details about programming the µDMA controller. SPRUH22I – April 2012 – Revised November 2019 M3 General-Purpose Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 306: Accessing Concatenated Register Values
8. Poll the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the appropriate bit of the GPTM Interrupt Clear Register (GPTMICR). M3 General-Purpose Timers SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 307: Real-Time Clock (Rtc) Mode
5. Load the timer start value into the GPTM Timer n Interval Load (GPTMTnILR) register. 6. If interrupts are required, set the CnEIM bit in the GPTM Interrupt Mask (GPTMIMR) register. SPRUH22I – April 2012 – Revised November 2019 M3 General-Purpose Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 308: 16-Bit Pwm Mode
GPTM Masked Interrupt 0x020 GPTMMIS 0x0000.0000 Status 0x024 GPTMICR 0x0000.0000 GPTM Interrupt Clear GPTM Timer A Interval 0x028 GPTMTAILR 0xFFFF.FFFF Load M3 General-Purpose Timers SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 309: Register Descriptions
GPTMCFG register. When in PWM mode, set the TAAMS bit , clear the TACMR bit, and configure the TAMR field to 0x2. SPRUH22I – April 2012 – Revised November 2019 M3 General-Purpose Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 310: Gptm Timer A Mode (Gptmtamr) Register
GPTM Timer A Mode. The timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register Reserved One-Shot Timer mode Periodic Timer mode Capture mode M3 General-Purpose Timers SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 311: Gptm Timer B Mode (Gptmtbmr) Register, Offset 0X008
Note: To enable PWM mode, you must also clear the TBCMR bit and configure the TBMR field to 0x1 or 0x2. TBCMR GPTM Timer B Capture Mode Edge-Count mode Edge-Time mode SPRUH22I – April 2012 – Revised November 2019 M3 General-Purpose Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 312: Gptm Control (Gptmctl) Register, Offset 0X00C
Timer B is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register. Reserved Reserved M3 General-Purpose Timers SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 313: Gptm Interrupt Mask (Gptmimr) Register, Offset 0X018
GPTM Timer B Mode Match Interrupt Mask Interrupt is disabled. Interrupt is enabled. CBEIM GPTM Capture B Event Interrupt Mask Interrupt is disabled. Interrupt is enabled. SPRUH22I – April 2012 – Revised November 2019 M3 General-Purpose Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 314: Gptm Raw Interrupt Status (Gptmris) Register, Offset 0X01C
The TBMIE bit is set in the GPTMTBMR register, and the match value in the GPTMTBMATCHR register has been reached when in the one-shot and periodic modes. M3 General-Purpose Timers SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 315: Gptm Masked Interrupt Status (Gptmmis) Register, Offset 0X020
TBTOMIS Reserved TAMMIS RTCMIS CAEMIS CAMMIS TATOMIS LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 M3 General-Purpose Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 316: Gptm Interrupt Clear (Gptmicr) Register, Offset 0X024
The GPTM Interrupt Clear (GPTMICR) register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1 to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers. M3 General-Purpose Timers SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 317: Gptm Timer A Interval Load (Gptmtailr) Register, Offset 0X028
16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBILR. SPRUH22I – April 2012 – Revised November 2019 M3 General-Purpose Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 318: Gptm Timer B Interval Load (Gptmtbilr) Register, Offset 0X02C
In a 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBMATCHR. M3 General-Purpose Timers SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 319: Gptm Timer B Match (Gptmtbmatchr) Register, Offset 0X034
Figure 2-18. GPTM Timer A Prescale (GPTMTAPR) Register Reserved TAPSR R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 M3 General-Purpose Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 320: Gptm Timer B Prescale (Gptmtbpr) Register, Offset 0X03C
The GPTM Timer B Prescale Match (GPTMTBPMR) register effectively extends the range of GPTMTBMATCHR to 24 bits when operating in 16-bit one-shot or periodic mode. M3 General-Purpose Timers SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 321: Gptm Timer A (Gptmtar) Register, Offset 0X048
Input Edge Count, Input Edge Time, and PWM modes, which is the upper 8 bits of the count. Bits 31:24 are reserved in both cases. SPRUH22I – April 2012 – Revised November 2019 M3 General-Purpose Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 322: Gptm Timer A Value (Gptmtav) Register, Offset 0X050
23:16 contain the current, free-running value of the prescaler, which is the upper 8 bits of the count. Bits 31:24 are reserved in both cases. M3 General-Purpose Timers SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 323: Gptm Timer B Value (Gptmtbv) Register
A read returns the current, free-running value of Timer A in all modes. When written, the value written into this register is loaded into the GPTMTAR register on the next clock cycle. SPRUH22I – April 2012 – Revised November 2019 M3 General-Purpose Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 324: M3 Watchdog Timers
........................... Topic Page ..................... Introduction ....................Register Map ..................Register Descriptions M3 Watchdog Timers SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 325: Introduction
System Clock/ WDTTEST OSCCLK Comparator WDTVALUE Identification Registers WDTPCellID0 WDTPeriphID0 WDTPeriphID4 WDTPCellID1 WDTPeriphID1 WDTPeriphID5 WDTPCellID2 WDTPeriphID2 WDTPeriphID6 WDTPCellID3 WDTPeriphID3 WDTPeriphID7 SPRUH22I – April 2012 – Revised November 2019 M3 Watchdog Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 326: Functional Description
Note that the watchdog timer module clock must be enabled before the registers can be programmed. See the System Control chapter, Run Mode Clock Gating Control Register 0 (RCGC0) section. M3 Watchdog Timers SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 327: Watchdog Load (Wdtload) Register
Value Description 31-0 WDTLOAD Watchdog load value Register not written. Value not loaded. Register written. Vlaue loaded and counter restarts. SPRUH22I – April 2012 – Revised November 2019 M3 Watchdog Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 328: Register Descriptions
Table 3-3. Watchdog Value (WDTVALUE) Register Field Descriptions Field Value Description 31-0 WDTVALUE Watchdog value. Current value of the 32-bit down counter. M3 Watchdog Timers SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 329: Watchdog Control (Wdtctl) Register, Offset 0X008
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-5. Watchdog Interrupt Clear (WDTICR) Register Field Descriptions Field Value Description 31-0 WDTINTCLR Watchdog interrupt clear SPRUH22I – April 2012 – Revised November 2019 M3 Watchdog Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 330: Watchdog Raw Interrupt Status (Wdtris) Register, Offset 0X010
The watchdog has not timed out or the watchdog timer interrupt is masked. A watchdog time-out event has been signalled to the interrupt controller. M3 Watchdog Timers SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 331: Watchdog Test (Wdttest) Register, Offset 0X418
A read of this register returns the following values: A watchdog time-out event has been signalled to the interrupt controller. 0x0000. Locked 0001 0x0000. Unlocked 0000 SPRUH22I – April 2012 – Revised November 2019 M3 Watchdog Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 332: Watchdog Peripheral Identification 4 (Wdtperiphid4) Register, Offset 0Xfd0
Table 3-12. Watchdog Peripheral Identification 6 (WDTPeriphID6) Register Field Descriptions Field Value Description 31-8 Reserved Reserved PID6 WDT Peripheral ID Register [23:16] M3 Watchdog Timers SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 333: Watchdog Peripheral Identification 7 (Wdtperiphid7) Register, Offset 0Xfdc
Table 3-15. Watchdog Peripheral Identification 1 (WDTPeriphID1) Register Field Descriptions Field Value Description 31-8 Reserved Reserved PID1 WDT Peripheral ID Register [15:8] SPRUH22I – April 2012 – Revised November 2019 M3 Watchdog Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 334: Watchdog Peripheral Identification 2 (Wdtperiphid2) Register, Offset 0Xfe8
Table 3-18. Watchdog PrimeCell Identification 0 (WDTPCellID0) Register Field Descriptions Field Value Description 31-8 Reserved Reserved CID0 Watchdog PrimeCell ID Register [7:0] M3 Watchdog Timers SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 335: Watchdog Primecell Identification 1 (Wdtpcellid1) Register, Offset 0Xff4
Table 3-21. Watchdog PrimeCell Identification 3 (WDTPCellID3) Register Field Descriptions Field Value Description 31-8 Reserved Reserved CID3 Watchdog PrimeCell ID Register [31:24] SPRUH22I – April 2012 – Revised November 2019 M3 Watchdog Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 336: General-Purpose Input/Output (Gpio)
See the General-Purpose Input/Output (GPIO) and C28 General-Purpose Input/Output (GPIO) sections of this chapter for more information..........................Topic Page ..............General-Purpose Input/Output (GPIO) ............C28 General-Purpose Input/Output (GPIO) General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 337: General-Purpose Input/Output (Gpio)
Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPUR=0, and GPIOPCTL=0). A Power-On-Reset (POR) or asserting XRS puts the pins back to their default state. SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 338: Gpio Pins And Alternate Functions
EPI0S25 PE4_GPIO28 CCP3 U2Tx CCP2 MII_RXD0 PE5_GPIO29 CCP5 PE6_GPIO30 PE7_GPIO31 PF0_GPIO32 CAN1Rx MII_RXCK PF1_GPIO33 CAN1Tx MII_RXER CCP3 PF2_GPIO34 MII_PHYINTRn SSI1Clk General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 339 USB0PFLT I2C1SDA PJ2_GPIO58 EPI0S18 CCP0 PJ3_GPIO59 EPI0S19 CCP6 PJ4_GPIO60 EPI0S28 CCP4 PJ5_GPIO61 EPI0S29 CCP2 PJ6_GPIO62 EPI0S30 CCP1 PJ7_GPIO63/ CCP0 XCLKIN SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 340: Gpio Pins And Alternate Mode Functions
MII_RXD1 U4Tx PG2_GPIO42 PG3_GPIO43 MII_RXDV TRACED1 PG5_GPIO45 PG6_GPIO46 PG7_GPIO47 PH0_GPIO48 SSI3Tx PH1_GPIO49 MII_RXD0 SSI3Rx PH2_GPIO50 SSI3Clk PH3_GPIO51 SSI3Fss PH4_GPIO52 U3Tx General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 341: Functional Description
GPIO blocks. Note that not all pins may be implemented on every block. Some GPIO pins can function as I/O signals for the on-chip peripheral modules. SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 342: Digital I/O Pads
GPIO port. When the data direction bit is set, the GPIO is configured as an output, and the corresponding data register bit is driven out on the GPIO port. General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 343: Gpiodata Write Example
GPIODATA + 0x0C4 yields as shown in . Figure 4-3. GPIODATA Read Example ADDR[9:2] 0x0C4 GPIODATA Returned V alue SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 344 The identification registers configured at reset allow software to detect and identify the module as a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as well as the GPIOPCellID0-GPIOPCellID3 registers. General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 345: Initialization And Configuration
Digital Input/Output (SSI) Digital Input/Output (UART) X=Ignored (don't care bit); ?=Can be either 0 or 1, depending on the configuration SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 346: Register Map
GPIO Port H (AHB): 0x4005.F000 • GPIO Port J (APB): 0x4003.D000 • GPIO Port J (AHB): 0x4006.0000 • GPIO Port K (AHB): 0x4006.1000 General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 347: Gpio Register Map
GPIOPeriphID0 0x0000.0061 GPIO Peripheral Identification 0 0xFE4 GPIOPeriphID1 0x0000.0000 GPIO Peripheral Identification 1 0xFE8 GPIOPeriphID2 0x0000.0018 GPIO Peripheral Identification 2 SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 348: Register Descriptions
Writes to this register only affect bits that are not masked by ADDR[9:2] and are configured as outputs. Section 4.1.3.2.2 for examples of reads and writes. General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 349: Gpio Direction (Gpiodir) Register
GPIO Interrupt Sense The edge on the corresponding pin is detected (edge-sensitive). The level on the corresponding pin is detected (level-sensitive). SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 350: Gpio Interrupt Both Edges (Gpioibe) Register
A falling edge or a Low level on the corresponding pin triggers an interrupt. A rising edge or a High level on the corresponding pin triggers an interrupt. General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 351: Gpio Interrupt Mask (Gpioim) Register
If a bit is clear, either no interrupt has been generated, or the interrupt is masked. SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 352: Gpio Masked Interrupt Status (Gpiomis) Register
Field Value Description 31-8 Reserved Reserved GPIO Interrupt Raw Status The corresponding interrupt is unaffected. The corresponding interrupt is cleared. General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 353: Gpio Alternate Function Select (Gpioafsel) Register
The associated pin functions as a GPIO and is controlled by the GPIO registers. The associated pin functions as a peripheral signal and is controlled by the alternate hardware function. SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 354: Gpio Open Drain Select (Gpioodr) Register
Figure 4-15. GPIO Pull-Up Select (GPIOPUR) Register Reserved Reserved R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 355: Gpio Digital Enable (Gpioden) Register
Pad Weak Pull-Up Enable The digital functions for the corresponding pin are disabled. The digital functions for the corresponding pin are enabled. SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 356: Gpio Lock (Gpiolock) Register
GPIOCR registers cannot be written with 0x0. These bits are hardwired to 0x1, ensuring that it is always possible to commit new values to the GPIOAFSEL, GPIOPUR, GPIOCSEL, or GPIODEN register bits of these other pins. General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 357: Gpio Commit (Gpiocr) Register
The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers. The analog function of the pin is enabled. Reserved Reserved SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 358: Gpio Port Control (Gpiopctl) Register
This field controls the configuration for GPIO pin 1. PMC0 Port Mux Control 0 This field controls the configuration for GPIO pin 0. General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 359: Gpio Alternate Peripheral Select (Gpioapsel) Register
Alternate peripheral mode disabled Alternate peripheral mode enable APSEL0 Alternate peripheral select 0 Alternate peripheral mode disabled Alternate peripheral mode enable SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 360: Gpio Core Select (Gpiocsel) Register
Selects M3 GPIO mux Selects C28 GPIO mux CSEL0 Core select 0 Selects M3 GPIO mux Selects C28 GPIO mux General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 361: Gpio Peripheral Identification 4 (Gpioperiphid4) Register
Table 4-25. GPIO Peripheral Identification 4 (GPIOPeriphID4) Register Field Descriptions Field Value Description 31-8 Reserved Reserved PID4 GPIO Peripheral ID Register [7:0] SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 362: Gpio Peripheral Identification 5 (Gpioperiphid5) Register
Table 4-26. GPIO Peripheral Identification 5 (GPIOPeriphID5) Register Field Descriptions Field Value Description 31-8 Reserved Reserved PID5 GPIO Peripheral ID Register [15:8] General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 363: Gpio Peripheral Identification 6 (Gpioperiphid6) Register
Table 4-27. GPIO Peripheral Identification 6 (GPIOPeriphID6) Register Field Descriptions Field Value Description 31-8 Reserved Reserved PID6 GPIO Peripheral ID Register [23:16] SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 364: Gpio Peripheral Identification 7 (Gpioperiphid7) Register
Table 4-28. GPIO Peripheral Identification 7 (GPIOPeriphID7) Register Field Descriptions Field Value Description 31-8 Reserved Reserved PID7 GPIO Peripheral ID Register [31:24] General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 365: Gpio Peripheral Identification 0 (Gpioperiphid0) Register
Reserved Reserved PID1 GPIO Peripheral ID Register [15:8] Can be used by software to identify the presence of this peripheral. SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 366: Gpio Peripheral Identification 2 (Gpioperiphid2) Register
32-bit register. The register is used as a standard cross- peripheral identification system. General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 367: Gpio Primecell Identification 0 (Gpiopcellid0) Register
Figure 4-33. GPIO PrimeCell Identification 2 (GPIOPCellID2) Register Reserved Reserved CID2 R-0x5h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 368: Gpio Primecell Identification 3 (Gpiopcellid3) Register
Table 4-36. GPIO PrimeCell Identification 3 (GPIOPCellID3) Register Register Field Descriptions Field Value Description 31-8 Reserved Reserved CID3 GPIO PrimeCell ID Register [31:24]. Provides software a standard cross-peripheral identification system. General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 369: C28 General-Purpose Input/Output (Gpio)
Analog Port 2 consists of AIO16-AIO31 Figure 4-35 through Figure 4-38 shows the basic modes of operation for the GPIO module. SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 370: Gpio0 To Gpio31 Multiplexing Diagram
GPIOs. If the GPIO is set as an M3 GPIO, the C28 GPIO MUX inputs are still active and can be read. General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 371: Gpio32, Gpio33 Multiplexing Diagram
The input qualification circuit is not reset when modes are changed (such as changing from output to input mode). Any state will get flushed by the circuit eventually. SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 372: Gpio34, Gpio135 Multiplexing Diagram
GPIOs. If the GPIO is set as an M3 GPIO, the C28 GPIO MUX inputs are still active and can be read. • The input qualification circuit is not reset when modes are changed (such as changing from output to General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 373: Analog/Gpio Multiplexing
SYNC (Read) AIODAT Reg (Latch) AIOMUX1 Reg AIOSET, AIOCLEAR, AIOTOGGLE Regs AIODIR Reg (Latch) (0 = Input, 1 = Output) SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 374: Gpio Mux-To-Trip Input Connectivity
Refer to the GPIO chapter for more information. The GPTRIPxSEL register must also be used to allow ECAP modules to capture data on a pin. Refer to the ECAP chapter for more information. General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 375: Configuration Overview
In Master Receive mode, a STOP condition should be generated only after a Data Negative Acknowledge executed by the master or an Address Negative Acknowledge executed by the slave. SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 376 GPxDIR registers. The output latch for all pins is cleared at reset. 7. Select low power mode wake-up sources: General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 377 NOTE: There is a 2-SYSCLKOUT cycle delay from when a write to configuration registers such as GPxMUXn and GPxQSELn occurs to when the action is valid SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 378: Digital General Purpose I/O Control
Only if the pin is later configured as a GPIO output, will the latched value be driven onto the pin. When using the GPxDAT register to change the level of an output pin, you should be cautious not to General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 379 Only if the pin is later configured as a GPIO output will the latched value will be driven onto the pin. Writing a 0 to any bit in the toggle registers has no effect. SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 380: Input Qualification
CPU clock (SYSCLKOUT). General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 381: Sampling Period
GPxCTRL[QUALPRDn] and the number of samples taken. SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 382: Case 1: Three-Sample Sampling Window Width
• Figure 4-41, the glitch (A) is shorter then the qualification window and will be ignored by the input qualifier. General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 383: Input Qualifier Clock Cycles
(5 x QUALPRD x 2) SYSCLKOUT cycles. That would ensure 5 sampling periods for detection to occur. Since external signals are driven asynchronously, an 13-SYSCLKOUT-wide pulse ensures reliable recognition. SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 384 Table 4-44 and the input would not be connected to GPIO5 or GPIO24. General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 385: Default State Of Peripheral Input
This value will be assigned to the peripheral input if more then one pin has been assigned to the peripheral function in the GPxMUX1/2 registers or if no pin has been assigned. SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 386: Gpioa Mux
This selection is a reserved configuration for future expansion. General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 387: Gpiob Mux
Reserved EPWM8A (O) 27-26 GPIO61 Reserved Reserved EPWM8B (O) 29-28 GPIO62 Reserved Reserved EPWM9A(O) 31-30 GPIO63/XCLKIN Reserved Reserved EPWM9B (O) SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 388: Gpioc Mux
Reserved Reserved 27-26 Not supported Reserved Reserved Reserved 29-28 Not supported Reserved Reserved Reserved 31-30 Not supported Reserved Reserved Reserved General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 389: Gpioe Mux
ADCINB2 (I), COMP4B (I) 23-22 ADCINB3 (I) ADCINB3 (I) 25-24 AIO28 (I/O) ADCINB4 (I), COMP5B (I) 27-26 ADCINB5 (I) ADCINB5 (I) SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 390 ADCINB6 (I), COMP6B (1) 31-30 ADCINB7 (I) ADCINB7 (I) Note: AIOMUX1 registers correspond to ADC1 and AIOMUX2 registers correspond to ADC2. General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 391: Gpio Port A Mux 1 (Gpamux1) Register
EPWM6A - ePWM6 output A (O) Reserved ADCSOCBO - ADC Start of conversion B (O) This register is EALLOW protected. SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 392 Configure the GPIO1 pin as: GPIO1 - General purpose I/O 1 (default) (I/O) EPWM1B - ePWM1 output B (O) ECAP - eCAP6 (I/O) Reserved General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 393: Gpio Port A Mux 2 (Gpamux2) Register
If reserved configurations are selected, then the state of the pin will be undefined and the pin may be driven. These selections are reserved for future expansion and should not be used. SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 394 Configure the GPIO18 pin as: GPIO18 - General purpose I/O 18 (default) (I/O) SPICLKA - SPI-A clock (I/O) Reserved Reserved General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 395: Gpio Port B Mux 1 (Gpbmux1) Register
Reserved Reserved Reserved 25:24 GPIO44 Configure this pin as: GPIO 44 - general purpose I/O 44 (default) Reserved Reserved Reserved SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 396 Configure this pin as: GPIO 35 - general purpose I/O 35 (default) SCITXDA - SCI - A transmit data (O) Reserved Reserved General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 397: Gpio Port B Mux 2 (Gpbmux2) Register
Configure this pin as: GPIO 61 - general purpose I/O 61 (default) Reserved Reserved EPWM8B - ePWM8 output B (O) SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 398 GPIO52 Configure this pin as: GPIO 52 - general purpose I/O 52 (default) EQEP1S - eQEP1 strobe (I/O) Reserved Reserved General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 399: Gpio Port C Mux 1 (Gpcmux1) Register
Reserved Reserved Reserved 13-12 GPIO70 Configure this pin as: GPIO 70 - general purpose I/O 70 (default) Reserved Reserved Reserved SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 400: Gpio Port E Mux 1 (Gpemux1) Register
Configure this pin as: GPIO 132 - general purpose I/O 132 (default) Reserved Reserved COMP3OUT - Comparator 3 output (O) General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 401: Analog I/O Mux 1 (Aiomux1) Register
Any writes to these bit(s) must always have a value of 0x2 AIO4 00 or 01 AIO4 enabled 10 or 11 AIO4 disabled (default) SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 402: Analog I/O Mux 2 (Aiomux2) Register
AIO18 enabled 10 or 11 AIO18 disabled (default) Reserved Any writes to these bit(s) must always have a value of 0xA General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 403: Gpio Port A Qualification Control (Gpactrl) Register
. . . 0xFF Sampling Period = 510 × T SYSCLKOUT This register is EALLOW protected. indicates the period of SYSCLKOUT. SYSCLKOUT SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 404: Gpio Port B Qualification Control (Gpbctrl) Register
4.2.7.11 GPIO Port C Qualification Control (GPCCTRL) Register The GPIO Port C Qualification Control (GPCCTRL) register is shown and described in the figure and table below. General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 405: Gpio Port C Qualification Control (Gpcctrl) Register
Note: GPIO on Port E is synchronized to the analog subsystem clock by default. indicates the period of SYSCLKOUT. SYSCLKOUT SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 406: Gpio Port A Qualification Select 1 (Gpaqsel1) Register
If the pin is configured as a GPIO input, then this option is the same as 0,0 or synchronize to SYSCLKOUT. This register is EALLOW protected. General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 407: Gpio Port B Qualification Select 1 (Gpbqsel1) Register
If the pin is configured as a GPIO input, then this option is the same as 0,0 or synchronize to SYSCLKOUT. This register is EALLOW protected. SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 408: Gpio Port C Qualification Select 1 (Gpcqsel1) Register
0,0 or synchronize to SYSCLKOUT. Any writes to these bit(s) must always have a value of 0. This register is EALLOW protected. General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 409: Gpio Port E Qualification Select 1 (Gpeqsel1) Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 410: Gpio Port B Direction (Gpbdir) Register
GPIO69 GPIO68 Reserved R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 411: Gpio Port E Direction (Gpedir) Register
Configures the GPIO pin as an input. (default) Configures the GPIO pin as an output This register is EALLOW protected. SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 412: Gpio Port E Pullup Disable (Gpepud)
Configures the AIO pin as an input. (default) Configures the AIO pin as an output General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 413: Gpio Port A Data (Gpadat) Register
Writing a 1will force an output of 1if the pin is configured as a GPIO output in the appropriate GPAMUX1/2 and GPADIR registers; otherwise, the value is latched but not used to drive the pin. SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 414: Gpio Port B Data (Gpbdat) Register
Writing a 1 will force an output of 1 if the pin is configured as a GPIO output in the GPBMUX1 and GPBDIR registers; otherwise, the value is latched but not used to drive the pin. General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 415: Gpio Port C Data (Gpcdat) Register
GPCDIR registers; otherwise, the value is latched but not used to drive the pin. Reserved Any writes to these bit(s) must always have a value of 0. SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 416: Gpio Port E Data (Gpedat) Register
Writing a 1 will force an output of 1 if the pin is configured as a GPIO output in the GPEMUX1 and GPEDIR registers; otherwise, the value is latched but not used to drive the pin. General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 417: Analog I/O Dat (Aiodat) Register
Writing a 1will force an output of 1if the pin is configured as a AIO output in the appropriate registers; otherwise, the value is latched but not used to drive the pin. SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 418: Gpio Port A Set, Clear And Toggle (Gpaset, Gpaclear, Gpatoggle) Registers
GPIO output then it will be driven in the opposite direction of its current state. If the pin is not configured as a GPIO output then the latch is toggled but the pin is not driven. General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 419: Gpio Port B Set, Clear And Toggle (Gpbset, Gpbclear, Gpbtoggle) Registers
GPIO output then the latch is cleared but the pin is not driven. SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 420: Gpio Port C Set, Clear And Toggle (Gpcset, Gpcclear, Gpctoggle) Registers
GPIO output then the latch is cleared but the pin is not driven. Reserved Any writes to these bit(s) must always have a value of 0. General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 421: Gpio Port E Set, Clear And Toggle (Gpeset, Gpeclear, Gpetoggle) Registers
GPIO output then the latch is cleared but the pin is not driven. SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 422: Analog I/O Toggle (Aioset, Aioclear, Aiotoggle) Register
AIO output then the latch is cleared but the pin is not driven. General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 423: Gpio Trip Input Select Register (Gptripxsel)
The GPIO Low Power Mode Wakeup Select 1 (GPIOLPMSEL1) register is shown and described in the figure and table below. SPRUH22I – April 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 424: Gpio Low Power Mode Wakeup Select 1 (Gpiolpmsel1) Register
If the respective bit is set to 1, the signal on the corresponding pin is able to wake the device from both HALT and STANDBY low power modes. This register is EALLOW protected. General-Purpose Input/Output (GPIO) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 425 This chapter provides information on the RAM and flash memory modules..........................Topic Page ..................RAM Control Module ................RAM Control Module Registers ................ Flash Controller Memory Module ....................Flash Registers SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 426: Ram Control
M3 subsystem are mapped to the M3 CPU and M3 µDMA. Similarly for the C28x subsystem, these RAM blocks are mapped to the C28 CPU and C28 DMA. Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 427: Shared Ram (Dedicated To Subsystem)
MSxSRCR register (when the RAM block is owned by the M3 subsystem) or the CSxSRCR register (when the RAM block is owned by the C28x subsystem). SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 428 – M3 byte access – two cycles (reads or byte writes takes two cycles of C28 clock when M3 clock config is /2 or /4 of C28 clock) – C28 Read – 1cycle – C28 Pread – 1 cycle Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 429 If a write access is made to a dedicated or shared memory by the master CPU and CPUWRPROTx is set to ‘1’ for that memory, it’s called a master CPU write protection violation. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 430 These errors are called correctable error and uncorrectable errors. Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 431 These need to be handled appropriately in software using the status and interrupt indications provided. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 432: Error Handling In Different Scenarios
The following table shows the bit mapping for the ECC/parity bits when they are read in RAMTEST mode using their respective addresses. Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 433: Mapping Of Ecc Bits In Read Data From Ecc/Parity Address Map
In case of Sx memory, the CPU of the subsystem, which is configured as the master for the particular Sx RAM block, can only initiate the RAM initialization. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 434: M3 Ram Configuration Registers Summary
Master Access Violation Flag Register MMAVCLR 0x68 Master Access Violation Flag Clear Register MNMWRAVADDR 0x70 Non-Master CPU Write Access Violation Address Register Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 435: C28X Ram Configuration Registers Summary
C28x Corrected Error Threshold Register CCEFLG 0x14 C28x C28x Corrected Error Threshold Exceeded Flag Register CEFRC 0x16 C28x C28x Corrected Error Threshold Exceeded Force Register SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 436 Register CMDMAWRAVADDR 0x3A C28x Master DMA Write Access Violation Address Register CMFAVADDR 0x3C C28x Master CPU Fetch Access Violation Address Register Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 437: Cx Dedram Configuration Register 1 (Cxdrcr1)
CPU Fetch Protection C0 M3 CPU Fetch allowed from C0 RAM block. M3 CPU Fetch not allowed from C0 RAM block. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 438: Cx Shram Configuration Register 1 (Cxsrcr1)
CPU Fetch Protection C2 M3 CPU Fetch allowed from C2 RAM block. M3 CPU Fetch not allowed from C2 RAM block. Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 439: Sx Shram Master Select Register (Msxmsel)
C28 subsystem is master for S1 RAM block. C28 CPU/DMA accesses are allowed based on the setting of protection bits in the CSxSRCR register. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 440: M3 Sx Shram Configuration Register 1 (Msxsrcr1)
µDMA Write Protection S2 M3 µDMA write allowed to S2 RAM block. M3 µDMA write not allowed to S2 RAM block. Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 441 CPU Fetch Protection S0 M3 CPU Fetch allowed from S0 RAM block. M3 CPU Fetch not allowed from S0 RAM block. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 442: M3 Sx Shram Configuration Register 2 (Msxsrcr2)
µDMA Write Protection S5 M3 µDMA write allowed to S5 RAM block. M3 µDMA write not allowed to S5 RAM block. Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 443 CPU Fetch Protection S4 M3 CPU Fetch allowed from S4 RAM block. M3 CPU Fetch not allowed from S4 RAM block. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 444: M3Toc28_Msg_Ram Configuration Register (Mtocmsgrcr)
Reserved Reserved DMAWRPROT µDMA Write Protection M3 µDMA write allowed to MTOC_MSG_RAM. M3 µDMA write not allowed to MTOC_MSG_RAM. Reserved Reserved Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 445: Cx Ram Test And Initialization Register 1 (Cxrtestinit1)
No action taken. Initialize all address locations of C0 RAM block with data 0x0 and corresponding data an address ECC/parity bits. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 446: M3 Sx Ram Test And Initialization Register 1 (Msxrtestinit1)
Initialize all address locations of S4 RAM block with data 0x0 and corresponding data an address ECC/parity bits. Applicabale only if M3 subsystem is master for S4 memory. Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 447 Initialize all address locations of S0 RAM block with data 0x0 and corresponding data an address ECC/parity bits. Applicabale only if M3 subsystem is master for S0 memory. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 448: Mtoc_Msg_Ram Test And Initialization Register (Mtocrtestinit)
MTOCMSGRAM No action taken. Initialize all address locations of MTOC_MSG_RAM block with data 0x0 and corresponding data and address ECC/parity bits. Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 449: Cx Ram Initdone Register 1 (Cxrinitdone1)
RAM initialization is done for C0 RAM block. C0 RAM can be accessed by M3 CPU. This status bit gets cleared when the RAMINIT bit is set for C0 RAM block. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 450: M3 Sx Ram Initdone Register 1 (Msxrinitdone1)
RAM initialization is done for S3 RAM block. S3 RAM can be accessed by M3 CPU/µDMA or C28x CPU/DMA. This status bit gets cleared when the RAMINIT bit is set for S3 RAM block. Reserved Reserved Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 451 RAM initialization is done for S0 RAM block. S0 RAM can be accessed by M3 CPU/µDMA or C28x CPU/DMA. This status bit gets cleared when the RAMINIT bit is set for S0 RAM block. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 452: Mtoc_Msg_Ram Initdone Register (Mtocrinitdone)
This register contains the address where uncorrectable error occurs during M3 µDMA byte writes. Only the address coresponding to the last error is stored. Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 453: M3 Cpu Uncorrectable Read Error Address Register (Mcuncreaddr)
This register contains the address where uncorrectable error occurs during M3 µDMA data read. Only the address coresponding to the last error is stored. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 454: M3 Cpu Corrected Read Error Address Register (Mcpucreaddr)
This register contains the address where correctable error occurs during M3 µDMA data read. Only the address coresponding to the last error is stored. Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 455: M3 Uncorrectable Error Flag Register (Mueflg)
M3 CPU uncorrectable write error occurred. Once this bit is set, it can be cleared by setting the corresponding error clear bit in the MUECLR register. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 456: M3 Uncorrectable Error Force Register (Muefrc)
M3 CPU Uncorrectable Write Error Force. Any reads to this bit will return a 0. Setting this bit to 1 will set the M3 CPU uncorrectable write error flag status. Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 457: M3 Uncorrectable Error Flag Clear Register (Mueclr)
MCEIE register. Note: Writing a value equal to the MCETRES generates an interrupt and sets the MCEFLG. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 458: M3 Corrected Error Threshold Register (Mcetres)
M3 Correctable Error Flag Force. Any read to this bit returns a 0. Setting this bit to 1 sets the MCEFLG flag in the MCEFLG register. Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 459: M3 Corrected Error Threshold Exceeded Flag Clear Register (Mceclr)
Correctable error interrupt is not generated even though the MCEFLG flag is set. Correctable error interrupt is generated when the MCEFLG flag is set. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 460: Non-Master Access Violation Flag Register (Mnmavflg)
31-3 Reserved Reserved CPUWRITE Non-Master CPU Write Access Violation Clear No effect. Clears the corresponding non-master DMA write access violation flag. Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 461: Master Access Violation Flag Register (Mmavflg)
Block for which FETCHPROT is set to 1. Once this bit is set, it can be cleared by setting the corresponding error clear bit in the MNMAVCLR register. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 462: Master Access Violation Flag Clear Register (Mmavclr)
Non-Master CPU Write Access Violation Address This holds the address at which M3 CPU attempted a write access and the non-master CPU write access violation occurred. Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 463: Non-Master Dma Write Access Violation Address Register (Mnmdmawravaddr)
Master CPU Write Access Violation Address This holds the address at which M3 CPU attempted a write access and the master CPU write access violation occurred. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 464: Master Dma Write Access Violation Address Register (Mmdmawravaddr)
Master CPU Fetch Access Violation Address This holds the address at which M3 CPU attempted a code fetch and the master CPU fetch access violation occurred. Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 465: Lx Dedram Configuration Register 1 (Lxdrcr1)
CPU Fetch Protection L0 C28x CPU Fetch allowed from L0 RAM block. C28x CPU Fetch not allowed from L0 RAM block. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 466: Lx Shram Configuration Register 1 (Lxsrcr1)
CPU Fetch Protection L2 C28x CPU Fetch allowed from L2 RAM block. C28x CPU Fetch not allowed from L2 RAM block. Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 467: C28X Sx Shram Master Select Register (Csxmsel)
C28 subsystem is master for S1 RAM block. C28 CPU/DMA accesses are allowed based on the setting of protection bits in the CSxSRCR register. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 468: C28X Sx Shram Configuration Register 1 (Csxsrcr1)
DMA Write Protection S2 C28x DMA write allowed to S2 RAM block. C28x DMA write not allowed to S2 RAM block. Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 469: C28X Sx Shram Configuration Register 2 (Csxsrcr2)
R/W-0 Reserved CPUWRPROT DMAWRPROT FETCHPROTS R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 470: C28X Sx Shram Configuration Register 2 (Csxsrcr2) Field Descriptions
CPU Fetch Protection S4 C28x CPU Fetch allowed from S4 RAM block. C28x CPU Fetch not allowed from S4 RAM block. Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 471: C28Toc28_Msg_Ram Configuration Register (Ctommsgrcr)
Reserved Reserved DMAWRPROT DMA Write Protection C28x DMA write allowed to CTOM_MSG_RAM. C28x DMA write not allowed to CTOM_MSG_RAM. Reserved Reserved SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 472: M0, M1 And C28T0C28_Msg_Ram Test And Initialization Register (C28Rtestinit)
No action taken. Initialize all address locations of M0 RAM block with data 0x0 and corresponding data an address ECC/parity bits. Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 473: Lx Ram Test And Initialization Register 1 (Clxrtestinit1)
No action taken. Initialize all address locations of L0 RAM block with data 0x0 and corresponding data an address ECC/parity bits. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 474: C28X Sx Ram Test And Initialization Register 1 (Csxrtestinit1)
RAMTEST feature is disabled for S4 RAM block. RAMTEST feature is enabled for S4 RAM block. ECC/parity logic is bypassed for memory accesses. Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 475 Initialize all address locations of S0 RAM block with data 0x0 and corresponding data an address ECC/parity bits. Applicable only if C28x subsystem is master for S0 memory. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 476: M0, M1 And C28T0M3_Msg_Ram Init Done Register (C28Rinitdone)
RAM initialization is done for M0 RAM block. M0 RAM can be accessed by M3 CPU. This status bit gets cleared when the RAMINIT bit is set for M0 RAM block. Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 477: C28X Lx Ram_Init_Done Register 1 (Clxrinitdone1)
RAM initialization is done for C0 RAM block. C0 RAM can be accessed by M3 CPU. This status bit gets cleared when the RAMINIT bit is set for C0 RAM block. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 478: C28X Sx Ram_Init_Done Register 1 (Csxrinitdone1)
RAM initialization is done for S3 RAM block. S3 RAM can be accessed by M3 CPU/µDMA or C28x CPU/DMA. This status bit gets cleared when the RAMINIT bit is set for S3 RAM block. Reserved Reserved Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 479 RAM initialization is done for S0 RAM block. S0 RAM can be accessed by M3 CPU/µDMA or C28x CPU/DMA. This status bit gets cleared when the RAMINIT bit is set for S0 RAM block. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 480: C28X Cpu Uncorrectable Read Error Address Register (Ccuncreaddr)
This register contains the address where correctable error occurs during C28x CPU data read or fetch. Only the address coresponding to the last error is stored. Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 481: C28X Dma Corrected Read Error Address Register (Cdmacreaddr)
C28x CPU uncorrectable read error occurred. Once this bit is set, it can be cleared by setting the corresponding error clear bit in the CUECLR register. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 482: C28X Uncorrectable Error Force Register (Cuefrc)
C28x CPU Uncorrectable Read Error Clear. Any reads to this bit will return a 0. No effect Clears the C28x CPU uncorrectable read error flag. Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 483: C28X Corrected Error Counter Register (Ccecntr)
C28x CPU/DMA Corrected Error Threshold Value If CCECNTR = CCETRES, correctable error interrupt gets generated if it is enabled in the CCEIE register. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 484: C28X Corrected Error Threshold Exceeded Flag Register (Cceflg)
C28x Correctable Error Flag Force. Any reads to this bit will return a 0. Setting this bit to 1 sets the CCEFLG flag in the CCEFLG register. Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 485: C28X Corrected Error Threshold Exceeded Flag Clear Register (Cceclr)
Correctable error interrupt is not generated even though the CCEFLG flag is set. Correctable error interrupt is generated when the CCEFLG flag is set. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 486: Non-Master Access Violation Flag Register (Cnmavflg)
RAM block for which M3 subsystem is the master. Once this bit is set, it can be cleared by setting the corresponding error clear bit in the CNMAVCLR register. Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 487: Non-Master Access Violation Force Register (Cnmavfrc)
Non-Master CPU Fetch Access Violation Clear. Any reads to this bit will return a 0. No effect. Clears the corresponding non-master CPU fetch access violation flag. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 488: Master Access Violation Flag Register (Cmavflg)
Master CPU Write Access Violation Force. Any reads to this bit will return a 0. No effect. Sets the CPUFETCH flag in the CNMAVFLG register. Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 489 Master CPU Fetch Access Violation Force. Any reads to this bit will return a 0. No effect. Sets the CPUFETCH flag in the CNMAVFLG register. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 490: Master Access Violation Flag Clear Register (Cmavclr)
Master CPU Fetch Access Violation Clear. Any reads to this bit will return a 0. No effect. Clears the corresponding master CPU fetch access violation flag. Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 491: Non-Master Cpu Write Access Violation Address Register (Cnmwravaddr)
Non-Master CPU Fetch Access Violation Address This holds the address at which C28x CPU attempted a code fetch and the non-master CPU fetch access violation occurred. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 492: Master Cpu Write Access Violation Address Register (Cmwravaddr)
Master CPU Fetch Access Violation Address This holds the address at which C28x CPU attempted a code fetch and the master CPU fetch access violation occurred. Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 493 Code Security Module to prevent access to the flash by unauthorized persons (refer to the System Control and Interrupts chapter for details) 5.3.2 Flash Tools Texas Instruments provides the following tools for flash: • Code Composer Studio V6.x - the development environment with integrated flash plugin •...
Page 494: Programmable Otp Locations In M3 Otp
Contents of this OTP location gets copied to the OTPSECLOCK register Z2_FLASH_ENTRY_POINT 0x68080C Alternate flash entry point can be programmed in this OTP location Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 495: Fmc Interface With Core, Bank And Pump
FMC to perform flash erase and program operations. The following sections (Section 5.3.6, Section 5.3.8, Section 5.3.8, Section 5.3.9, and Section 5.3.10) will describe FMC in detail. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 498: Flash Cache Mode
8 x 128-bit 128-bit prefetch data Direct mapped program cache Instruction fetch Cortex 32-bit 128-bit data cache Data from DCODE access Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 499 1s and the respective zone is not unlocked. • ICODE accesses to zone-1 and zone-2 password locations return a 0 when the respective password SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 500 BANZ, call, or loop. When this occurs, the prefetch is aborted and the contents of the prefetch buffer are flushed. There are two possible scenarios when this occurs: Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 501: Flash Prefetch Mode
If C28x security zone is in the locked state and the respective password lock bits are not all 1s, then, – Data reads to C28X-Z1-CSMPSWD, C28x-Z1-ECSLPSWD will return 0. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 502 NOTE: The read-margin modes are intended for diagnostic capabilities. Flash content is guaranteed for the lifetime specified in the datasheet. Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 503 The Flash API uses hardware ECC logic in the device to generate the ECC data for the given flash data. The Flash plugin and UniFlash use Flash APIs to generate and program ECC data. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 504: Ecc Logic Inputs And Outputs
ECC logic will be bypassed when the 64 data bits and the associated ECC bits fetched from the bank are either all ones or zeros. Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 505 They will not occur for the other 64 bits that do not have an uncorrectable error in the 128-bit memory aligned data. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 506 When allocating code and data to flash and OTP memory, keep the following reserved locations of flash/OTP in mind: • M3 OTP has reserved locations for OTPSECLOCK, Zone 2 Flash entry point and EMAC ID whose Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 507 CPU pipeline. This must be done before the return-from-function call is made. 5. Return to the calling function which might reside in RAM or Flash/OTP and continue execution. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 508: Flash Registers Memory Map On Master Subsystem
Status Register (Used with Flash API – Refer to Flash Application Programming Interface User’s Specification for details of this register) Reserved Reserved Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 509: Flash Registers Memory Map On Control Subsystem
Table 5-85. Flash Registers Memory Map on Control Subsystem Register Register Size (x8) Type C28x offset C28x Protection Reset source Acronym Description (0x8) Flash Control Registers 0x4000 SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 510 Clear Register ERR_CNT Error Counter EALLOW C28SYSRSTn Register ERR_THRESHO Error Threshold EALLOW C28SYSRSTn Register ERR_INTFLG Error Interrupt 0x10 EALLOW C28SYSRSTn Flag Register Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 511 C28SYSRSTn TEST High Register FECC_FOUTL_ Test Data Out 0x20 EALLOW C28SYSRSTn TEST Low Register FECC_STATUS ECC Status 0x22 EALLOW C28SYSRSTn Register SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 512: Flash Read Control Register (Frdcntl)
Read Margin 1 mode is disabled Read Margin 1 mode is enabled Read Margin 0 mode is disabled Read Margin 0 mode is enabled Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 513: Flash Bank Access Control Register (Fbac)
Note: If the bank and pump are not in active mode and an access is made, the value of this register is automatically changed to active. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 514: Flash Bank Pump Control Register (Fbprdy)
PSLEEP = PSLEEP_REQ_ns / 2 / HCLK_period_ns PSLEEP = 20000/2/6.66 (in decimal) 15-1 Reserved Reserved Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 515: Flash Bank Pump Control Register 2 (Fpac2)
BANKID. Controls the bank on which the Flash FSM operations will be performed. For these devices, the value of this field will be 0 as there is only one bank in Master subsystem. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 516: Seczonerequest(Sem) Register
Also, if sectors belonging to zone2 needs to be programmed or erased then SEM should be 10 or zone2 needs to be unlocked. Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 517: Flash Read Interface Control Register (Frd_Intf_Ctrl)
Prefetch enable. A value of 0 disables program cache and prefetch mechanism. A value of 1 enables program cache and prefetch mechanism. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 518: Ecc Enable Register (Ecc_Enable)
Table 5-98. Uncorrectable Error Address Register (UNC_ERR_ADDR) Field Descriptions Field Value Description 31-0 UNC_ERR_ADD Address at which an un-correctable error occurred, aligned to a 64-bit boundary Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 519: Error Status Register (Err_Status)
ERR_TYPE bit indicates a check bit or a data bit. If ERR_TYPE indicates a check bit error, the error position could range from 0 to 7, else it could range from 0 to 63. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 520: Error Status Clear Register (Err_Status_Clr)
ECC logic test mode, ECC logic test mode has to be disabled prior to clearing the ERR_CNT using "Single Err Int Clear" bit. Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 521: Error Threshold Register (Err_Threshold)
SINGLE_ERR_INT interrupt is fired. When SINGLE_ERR_INT_CLR bit of ERR_INTCLR register is written a value of 1 this bit is cleared. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 522: Error Interrupt Flag Clear Register (Err_Intclr)
31-0 FDATAL Low double word of selected 64-bit data. User-configurable bits 31:0 of the selected data blocks in ECC test mode. Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 523: Ecc Test Address Register (Faddr_Test)
Selects the ECC block on bits [127:64] of bank data. ECC_TEST_EN ECC test mode enable. ECC test mode disabled ECC test mode enabled SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 524: Test Data Out High Register (Fecc_Fouth_Test)
SINGLE_ERR Test mode ECC single bit error. When 1 indicates that the ECC test resulted in a single bit error. Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 525: Flash Read Control Register (Frdcntl)
Read Margin 1 mode is disabled Read Margin 1 mode is enabled Read Margin 0 mode is disabled Read Margin 0 mode is enabled SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 526: Flash Bank Access Control Register (Fbac)
Note: If the bank and pump are not in active mode and an access is made, the value of this register is automatically changed to active. Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 527: Flash Bank Pump Control Register (Fbprdy)
Note: The pump sleep down counter uses the same prescaled clock as Bank sleep down counter which is divided by 2 of input SYSCLK. 15-1 Reserved Reserved SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 528: Flash Bank Pump Control Register 2 (Fpac2)
Figure 5-118. Flash Read Interface Control Register (FRD_INTF_CTRL) Reserved DATA_CACHE_EN PROG_CACHE_EN R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 529: Ecc Enable Register (Ecc_Enable)
Table 5-125. Uncorrectable Error Address Register (UNC_ERR_ADDR) Field Descriptions Field Value Description 31-0 UNC_ERR_ADD Uncorrectable error address. Address at which un-correctable error occurred, aligned to a 128 bit boundary. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 530: Error Status Register (Err_Status)
ERR_TYPE bit indicates a check bit or a data bit. If ERR_TYPE indicates a check bit error, the error position could range from 0 to 7 else it could range from 0 to 63. Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 531: Error Status Clear Register (Err_Status_Clr)
Figure 5-126. Error Threshold Register (ERR_THRESHOLD) 16 15 Reserved THRESHOLD R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 532: Error Interrupt Flag Register (Err_Intflg)
Single bit error interrupt flag clear. Writing a 1 to this bit will clear SINGLE_ERR_INT_FLG. Writes of 0 have no effect. Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 533: Data High Test Register (Fdatah_Test)
Figure 5-132. ECC Test Register (FECC_TEST) Reserved R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 534: Ecc Control Register (Fecc_Ctrl)
Figure 5-135. Test Data Out Low Register (FECC_FOUTL_TEST) DATAOUTL LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Internal Memory SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 535: Ecc Status Register (Fecc_Status)
SINGLE_ERR Test mode ECC single bit error. When 1 indicates that the ECC test resulted in a single bit error. SPRUH22I – April 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 536 ................... C-Boot ROM Description ............Guidelines for Boot ROM Application Writers ..............Application Notes to Use Boot ROM ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 537 – Use one of the available IPC commands to ask C-Boot ROM to boot from the control subsystem peripherals. SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 538: Master Subsystem Boot Mode Selection
(bits 0:7), bmode_pin2 (bits 8:15), Bmode_pin3 (bits 16:23), and bmode_pin4 (bits 24:31). OTP BOOTMODE GPIO CONFIG REGISTER at 0x680824 location. ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 539 Selecting these pins as boot mode pins is considered an illegal GPIO entry. SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 540: Device Boot Flow
Read Boot Mode GPIO Master subsystem boot as per boot mode ACIB interface ready ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 541: M-Boot Rom Memory Map
Reset (1) 0x00000004 ResetISR Non-Maskable Interrupt(2) 0x00000008 mbrom_nmi_interrupt_handler Hard Fault (3) 0x0000000C mbrom_hard_fault_isr_handler Memory Management (4) 0x00000010 IntDefaultHandler SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 542: M-Boot Rom Version And Checksum Information
RAM for the first time to avoid any ECC and Parity errors. Refer to the Internal Memory chapter for more details on RAM ECC and Parity. ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 543: Rev0 - User Configurable Dcsm Otp Fields
ECC is shared for these fields, so they must be programmed at the same time. 0x68080C Z2 FLASH ENTRY POINT SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 544: M-Boot Rom Entry Points
0x20005000 in C2 RAM. User applications which use this option must have their main function located at this address or have a branch to main() instruction at this location. ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 545 This entry point will be referred to as M_BOOT_FROM_I2C0_MASTER_MODE_ENTRY_POINT in this document. Please refer to Section 6.5.15.1.3 for more details on I2C0 boot load protocol. SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 546: M-Boot Rom Clock Settings
0(default) 0(default) Master(default) Input PA3_GPIO3 0(default) 0(default) Master(default) Input PA4_GPIO4 0(default) 0(default) Master(default) Input PA5_GPIO5 0(default) 0(default) Master(default) ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 547 If the source of the reset is POR, initialize all RAMs (Cx RAM, SxRAM, M2CMSGRAM) to 0x0000 • If the source of the reset is NOT POR, zero-out stack used for boot ROM SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 548 • Reset device configuration set up by M-Boot ROM for boot purposes. – Disable clock to all peripherals ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 549 Branch to the entry point address 6.5.11 M-Boot ROM Flow Diagram The M-Boot ROM flow diagram is shown below. SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 550: M-Boot Rom Flow Diagram
PORn and XRSn appropriately C-BootROM Bring control system out of reset Bring Analog system/CIB A-BootROM out of reset M_M3_1 ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 551 NOTE: Boot-to-OTP option is not shown in this flow chart, but it is similar to boot-to-RAM option. The boot-ROM upon decoding the boot-to-OTP option from the boot-mode GPIO pins jumps to the M_BOOT_ROM_OTP_ENTRY_POINT. SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 552: M-Boot Rom Boot Status
If set, M-BootROM detected a C28 BIST ERR NMI If set, M-BootROM detected a M3 BIST ERR NMI If set, M-BootROM detected a Missing clock NMI ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 553: M-Boot Rom Reset Cause Handling
Log the error in boot status and configure WDT0 and loop and let device reset on WDT0 timeout. SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 554 PA3_GPIO3, peripheral MODE -1 SSI0_CLK PA2_GPIO2, peripheral MODE -1 SSI0_TX PA5_GPIO5, peripheral MODE -1 SSI0_RX PA4_GPIO4, peripheral MODE -1 ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 555 This allows the sender to re-transmit the previous packet. SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 556: M-Boot Rom Serial Boot Commands
COMMAND_GET_STATUS is sent to the microcontroller. COMMAND_RET_SUCCESS (= 0x40) COMMAND_RET_UNKNOWN_CMD (= 0x41) ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 557 The below function call sequence gives details of the flow when serial boot mode is selected on the device. • ResetIsr() • mbrom_init_device() • mbrom_master_system_init () • mbrom_control_system_init() SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 558 UART connection. The I2C interface also provides a standard interface, only uses two wires, and can operate at comparable speeds to the UART and SSI interfaces. ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 559 By using standard protocols, the bootloader will co-exist in a normal Ethernet environment without causing any problems (other than using a small amount of network bandwidth). SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 560 CUSTOMER_OTP_EMAC_REG1_ADDR = 0x680814 A MAC address of 12:34:56:78:9A:BC should get stored/programmed as: CUSTOMER_OTP_EMAC_REG0_ADDR = 0x00563412 CUSTOMER_OTP_EMAC_REG1_ADDR = 0x00BC9A78 ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 561 6.5.15.3.2 M-Boot ROM CAN Interface IO CAN0_RX - PB4_GPIO12, peripheral MODE -5 CAN0_TX - PB5_GPIO13, peripheral MODE -5 SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 562: M-Boot Rom Can Boot Commands
= Data[2]; ucData[3] = Data[3]; ucData[4] = Data[4]; ucData[5] = Data[5]; ucData[6] = Data[6]; ucData[8] = Data[7]; ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 563 M-Boot ROM WIR Mode Check – Please refer to WIR Mode section in System Control and Interrupts chapter. • mbrom_get_bootmode() – ConfigureCAN(); • UpdaterCAN(); SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 564: Overview Of Parallel Gpio Bootloader Operation
(LSB). In this case, data is read from GPIO[9,8,5:0]. The 8-bit data stream is shown in Table 6-13. ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 565: Parallel Gpio Bootloader Handshake Protocol
This process is repeated for each data value to be sent. Figure 6-7 shows an overview of the Parallel GPIO bootloader flow. SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 566: Parallel Gpio Mode Overview
ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 567: Parallel Gpio Mode - Host Transfer Flow
MSB and LSB into a single 16-bit value to be passed back to the calling routine. SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 568: 8-Bit Parallel Getword Function
M-Boot ROM WIR Mode Check – Please refer to WIR Mode section in the System Control and Interrupts chapter. • mbrom_get_bootmode() – o Parallel_Boot(); • mbrom_start_app(M_BOOT_ROM_PARALLEL_BOOT_MODE_ENTRY_POINT) ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 569 If the user wishes to lock the main clock frequency at 20 MHz, then the OTP location must be programmed with 0x00000000. SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 570 ROM. The memory block is 32Kx16 in size and is located at 0x3F 8000 - 0x3F FFFF in both program and data space. ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 571: C-Boot Rom Memory Map
SARAM space. The floating-point math tables included in the boot ROM are used by the Texas Instruments™ C28x FPU Fast RTS Library (SPRC664). The C28x Fast RTS Library is a collection of optimized floating-point math functions for C programmers of the C28x with floating-point unit.
Page 572 > FPUTABLES, PAGE = 0, TYPE = NOLOAD, The fixed-point math tables included in the boot ROM are used by the Texas Instruments™ C28x™ IQMath Library - A Virtual Floating Point Engine (SPRC087). The 28x IQmath Library is a collection of highly optimized and high precision mathematical functions for C/C++ programmers to seamlessly port a floating-point algorithm into fixed-point code on TMS320C28x devices.
Page 573 – Contents: Coefficient table to calculate the formula f(x) = c4*x^4 + c3*x^3 + c2*x^2 + c1*x + c0. SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 574: C-Boot Rom Version And Checksum Information
PIE interrupt vector fetch, in which case C- Boot ROM sends an IPC message to the master subsystem as shown in Section 6.6.12.2 Section 6.6.1.3. ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 575: C-Boot Rom Vector Table Map
INT3 0x003FFFC6 0x00000046 INT4 0x003FFFC8 0x00000048 INT5 0x003FFFCA 0x0000004A INT6 0x003FFFCC 0x0000004C INT7 0x003FFFCE 0x0000004E INT8 0x003FFFD0 0x00000050 SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 576: Pie Vector Table In C-Boot Rom
INT2 (2) – INT14 (14) 0x00000D04 – 0x00000D1C cbrom_pie_isr_not_supported DLOGINT (15) 0x00000D1E cbrom_pie_isr_not_supported RTOSINT (16) 0x00000D20 cbrom_pie_isr_not_supported EMUINT (17) 0x00000D22 cbrom_pie_isr_not_supported ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 577 If code is bootloaded into this region there is no error checking to prevent it from corrupting the boot ROM stack. SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 578: C-Boot Rom Boot Modes
IPC commands is explained in detail in the subsequent sections of this chapter. Refer to Section 6.7 for more details on this procedure. ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 579: C-Boot Rom Entry Point
Entry point in this boot mode will be provided by the user or host system which is sending boot code to the device. Please refer to I2C Boot Data format for more details. SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 580 GPIOs used for each boot mode on C-Boot ROM. More details on the boot mode is given further below in this document. ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 581: C-Boot Rom Gpio Assignments For Boot Modes
Put CPU in C28x Object Mode • If POR is the source of reset, initialize M0, M1, L0-L3 and CTOM MSGRAM to 0x0 SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 582 Set Boot Status for Master applications to read • Enter Low Power IDLE mode. The C-Boot ROM flow chart is shown below. ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 583: C-Boot Rom Flow Chart
EMU1==1 handler at @0x3FFFBE Install MTOCIPCINT1 Enable PIE Go to IDLE mode; Wake up to handle IPC interrupts SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 584 MTOCIPCFLG[0] is cleared by C-Boot ROM, in error cases. Figure 6-13 shows the procedure to be followed by the master subsystem application. ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 585: Master Subsystem Application Procedure To Send Ipc To C-Boot Rom
<to clear the IPCFLG which is not cleared by C-Boot ROM> 6.6.9.2 Procedure Followed by C-Boot ROM to Handle IPC Commands From Master - SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 586 Figure 6-14 explains how C-Boot ROM MTOCIPCINT1 handler - cbrom_mtoc_ipc_int1_isr, follows to service IPC command from Master. ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 587: C-Boot Rom Handling On Mtocipc
IDLE Mode Handling another IPC == FALSE Branch Command or Boot Command Branch address or boot app address SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 588: Mtoc Ipc Commands
Data read back 0x00 = Command EALLOW; _WRITE_PROTECTED_16 bit register MTOCIPCDATAW[ from the address success *(address) = data; 15:0] EDIS; ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 590: C-Boot Rom Nak/Error Status Returns For Mtocipccom
Note: The rest of the bits are reserved and user applications don’t care if these bits are set or reset. ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 591: C-Boot Rom Health Status
ROM. For ex: if MTOCIPCBOOTSTS == C_BOOTROM_BOOTSTS_CTOM_CONTROL_SYSTEM_READY, it means that C-Boot ROM is ready to accept MTOC IPC commands. SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 592: Ctom Ipc Messages
C-Boot ROM is waiting for a reset from the master subsystem, when this even occurs ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 593: C-Boot Rom Exceptions Handling
CTOMBOOTSTS register, send IPC message to master and wait in while(1) loop for master to handle the error state.. SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 594 For an 8-bit data stream, the key value is 0x08AA and for a 16-bit stream it is 0x10AA. If a bootloader receives an invalid key value, then the load is aborted. ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 595 Execution will then continue at the entry point address as determined by the input data stream contents. SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 596: General Structure Of Source Program Data Stream In 16-Bit Mode
Last word of the last block of the source being loaded Block size of 0000h - indicates end of the source program ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 597 (LSW). The bootloaders take this into account when loading an 8-bit data stream. SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 598: Lsb/Msb Loading Sequence In 8-Bit Data Stream
MSB: Last word of the last block LSB: 00h MSB: 00h - indicates the end of the source ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 599 8-bit or 16-bit key value, or if the value is not valid for the given boot mode then the load will abort. SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 600: Bootloader Basic Transfer Procedure
See the info specific to a particular bootloader for any limitations. In 8-bit mode, the LSB of the 16-bit word is read first followed by the MSB. ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 601: Overview Of Copydata Function
ROM SCITXDA source) The SCI-A loader uses following pins: • SCIRXDA on GPIO36 • SCITXDA on GPIO35 SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 602: Overview Of Sci_Boot Function
Disable SCI FIFOs Prime SCI-A baud register Read EntryPoint address Enable autobaud detection Call CopyData Autobaud lock Return EntryPoint ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 603: Overview Of Sci_Getworddata Function
SCIA_GetWordData Received Read LSB Data Echoback LSB Received to host Read MSB Echoback MSB Return MSB:LSB to host SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 604: Spi Loader
Data for this section. Blocks of data in the format size/destination address/data as shown in the generic data stream description ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 606: Data Transfer From Eeprom Flow
Figure 6-23. Overview of SPIA_GetWordData Function Data Send dummy SPIA_GetWordData Received character Read LSB Data Send dummy Received character Read MSB Return MSB:LSB ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 607: Eeprom Device At Address 0X50
The input frequency to the device must be in the appropriate range. • The EEPROM must be at slave address 0x50. SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 608: Overview Of I2C_Boot Function
(I2C_Get Word). If a non acknowledgment is received during the data read messages, the I2C bus will hang. Table 7-3 shows the 8-bit data stream used by the I2C. ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 609: Random Read
Figure 6-27. Sequential Read SDA LINE 0 0 0 1 0 Device DATA BYTE n DATA BYTE n+1 Address SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 610: Overview Of Parallel Gpio Bootloader Operation
(LSB). In this case, data is read from GPIO[9,8,5:0]. The 8-bit data stream is shown in Table 6-30. ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 611: Parallel Gpio Bootloader Handshake Protocol
This process is repeated for each data value to be sent. Figure 6-30 shows an overview of the Parallel GPIO bootloader flow. SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 612: Parallel Gpio Mode Overview
ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 613: Parallel Gpio Mode - Host Transfer Flow
(MSB). It then combines the MSB and LSB into a single 16-bit value to be passed back to the calling routine. SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 614: 8-Bit Parallel Getword Function
The flow diagrams and procedures listed below in this section explain the minimum things that should be done in order to successfully boot the control subsystem. ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 615: Master Subsystem Application Flow To Start C-Boot Rom Loaders
ODE = MTOCIPCBOOTMODE ODE = ODE = ODE = = BOOT_FROM_RAM BOOT_FROM_PAR BOOT_FROM_SCI BOOT_FROM_I2C BOOT_FROM_SPI ALLEL MTOCIPCSET = 0x80000001 SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 616 Disclaimer:- Copyright (c) 2008-2011 Texas Instruments Incorporated. All rights reserved. Software License Agreement Texas Instruments (TI) is supplying this software for use solely and exclusively on TI's microcontroller products. The software is owned by TI and/or its suppliers, and is protected under applicable copyright laws.
Page 617 Function called to Zero-Initialize control subsystem L0, L1, L2, L3 RAM memories using MTOCIPC commands to C-Boot ROM void master_ram_init_control_L0_L3_memories() unsigned int ii = 0; //RAM INIT for L0,L1,L2,L3 SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 618 //GIVE some cycles delay until CCORE performs RAM INIT for(ii =0 ; ii < 2048; ii++); continue; }while(1); ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 619: Build A Binary Image For Bootload Using M-Boot Rom
This COFF file is given as input to the above scripts to generate a final plain binary image that can be used (as shown in the following section), to send data to M-Boot ROM. SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 620: Lm Flash Programmer Configuration Screen
2. Select either UART or Ethernet interface as shown below, depending on which interface he is using to boot load data. ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 621: Lm Flash Programmer Interface Selection Screen
6.8.1.2.1 Using the LM FLASH Programmer to Send Data to the M-Boot ROM UART0 Interface – Serial Bootload Option 1. Select the UART interface and configure the HOST COM Port Baud Rate as needed. SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 622: Lm Flash Programmer Serial Interface Configuration Screen
MCU, but will send the RESET packet to the M-Boot ROM bootloader which will start executing the application code just downloaded. ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 623: Lm Flash Programmer Binary Image Selection Screen
Concerto device, and the Client IP Address field should be filled with a proper IP address that the user wants to assign to the device. SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 624: Lm Flash Programmer Emac Interface Selection Screen
Note: There is no way for the user to control where in the master subsystem RAM, the application should get loaded. It is fixed at M_BOOT_ROM_RAM_ENTRY_POINT as explained in Section 6.5.7.5 ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 625: Flash Programmer Emac Bootload Binary Image Selection Screen
It can be useful to check this file to make sure SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 626: Bootloader Options
The first origin listed for each output section is the starting address of that entire output section. The following origin values are the starting address of that portion of the output section. ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 627 Use the GPIO in 8-bit mode data format. The eCAN uses the same data format as the GPIO in 8-bit mode. Select ASCII-Hex as the output format. SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 628 Entrypoint address that was read as part of the data stream. In this case, execution will begin at 0x3FA0000. ROM Code and Peripheral Booting SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 629 00 00 00 00 ;Data = 0x0000, 0x0000 00 00 ;Block size of 0 - end of data SPRUH22I – April 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 630 ........................... Topic Page ..................... Introduction ................... ePWM Submodules ..............Applications to Power Topologies ......................Registers C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 632 Each ePWM module is connected to the input/output signals shown in Figure 7-1. The signals are described in detail in subsequent sections. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 633: Multiple Epwm Modules
Each ePWM module consists of eight submodules and is connected within a system via the signals shown in Figure 7-2. SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 634: Submodules And Signal Connections For An Epwm Module
Whichever event triggers the start of conversion is configured in the Event-Trigger submodule of the ePWM. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 635: Epwm Submodules And Critical Internal Signal Interconnects
Each submodule is described in detail in its respective section. SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 636 7-1. Each register set is duplicated for each instance of the ePWM module. The start address for each ePWM register file instance on a device is specified in the appropriate data manual. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 637: Epwm Module Control And Status Register Set Grouped By Submodule
These registers only exist in the ePWM1 register space. They cannot be accessed from any other ePWM module's register space. SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 638 0x70-0x7F contains dual-mapped frequently-used control registers from lower page in order to accommodate minimal DP pointer switching. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 639: Epwm Module Control And Status Register Set Grouped By Submodule (Upper Page)
[if exisiting] and their behaviour in shadow/immediate mode with respect to a Read or Write operation. In Immediate Mode: SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 640 DBFED 0x11 Shadow Shadow DBFEDM 0x53 Shadow Shadow CMPC 0x69 Shadow Shadow CMPD 0x6B Shadow Shadow C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 641: Submodule Configuration Parameters
• Bypass the PWM-chopper module entirely. In this case the PWM waveform is passed through without modification. SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 642 These examples use the constant definitions in the device EPwm_defines.h file in the device-specific header file and peripheral examples software package. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 643: Time-Base Submodule
Configure the rate of the time-base clock; a prescaled version of the CPU system clock (SYSCLKOUT). This allows the time-base counter to increment/decrement at a slower rate. SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 644: Time-Base Submodule Registers
Width Modulator (HRPWM) section of this manual. Refer to the device-specific data manual to determine which ePWM instances include this feature. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 645: Time-Base Submodule Signals And Registers
This signal is generated whenever the counter value is zero. That is when TBCTR equals 0x00. SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 646 When it reaches zero, the time-base counter is reset to the period value and it begins to decrement once again. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 647: Time-Base Frequency And Period
PRDLDSYNC bit is valid only if TBCTL[PRDLD] = 0. By default the TBPRD shadow register is enabled. The sources for the SYNC input is explained in Time-Base Counter Synchronization section SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 648: Time-Base Counter Synchronization Scheme 4
Please refer to the device specific data manual to determine which modules are available on a particular device. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 649 2. Set TBCLKSYNC = 0. This will stop the time-base clock within any enabled ePWM module. 3. Configure the prescaler values and desired ePWM modes. 4. Set TBCLKSYNC = 1. SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 650 To illustrate the operation of the first three modes, the following timing diagrams show when events are generated and how the time-base responds to an EPWMxSYNCI signal. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 651: Time-Base Up-Count Mode Waveforms
TBCTR[15:0] 0xFFFF TBPRD (value) TBPHS (value) 0000 EPWMxSYNCI CTR_dir CTR = zero CTR = PRD CNT_max SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 652: Time-Base Down-Count Mode Waveforms
(value) TBPHS (value) 0x0000 EPWMxSYNCI CTR_dir DOWN DOWN DOWN CTR = zero CTR = PRD CNT_max C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 653: Time-Base Up-Down Count Waveforms, Tbctl[Phsdir = 1] Count Up On Synchronization Event
Digital Compare PIEERR (DC) Signals COMPxOUT GPTRIP Figure 7-13 shows the basic structure of the counter-compare submodule. SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 654: Counter-Compare Submodule Registers
Modulator (HRPWM) section of this manual. Refer to the device-specific data manual to determine which ePWM instances include this feature. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 655: Detailed View Of The Counter-Compare Submodule
TBCTR = CMPC CTR = CMPD Time-base counter equal to the active counter-compare D value TBCTR = CMPD SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 656 1. CTR = CMPC: Time-base counter equal to counter-compare C register (TBCTR = CMPC). 2. CTR = CMPD: Time-base counter equal to counter-compare D register (TBCTR = CMPD). C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 657 Figure 7-14 through Figure 7-17 show when events are generated and how the EPWMxSYNCI signal interacts. SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 658: Counter-Compare Event Waveforms In Up-Count Mode
This can lead to a compare event being skipped. This skipping is considered normal operation and must be taken into account. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 659: Counter-Compare Events In Down-Count Mode
TBPRD (value) CMPA (value) CMPB (value) TBPHS (value) 0x0000 EPWMxSYNCI CTR = CMPA CTR = CMPB SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 660: Counter-Compare Events In Up-Down-Count Mode, Tbctl[Phsdir = 0] Count Down On Synchronization Event
7.2.4 Action-Qualifier (AQ) Submodule Figure 7-18 shows the action-qualifier (AQ) submodule (see shaded block) in the ePWM system. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 661: Action-Qualifier Submodule
Action Qualifier Control Mirror Register For Output B AQSFRCM 0x75 Action Qualifier Software Force Mirror Register SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 662: Action-Qualifier Submodule Inputs And Outputs
The possible actions imposed on outputs EPWMxA and EPWMxB are: • Set High: Set output EPWMxA or EPWMxB to a high level. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 663: Possible Action-Qualifier Actions For Epwmxa And Epwmxb Outputs
TB Counter equals: Actions force Comp Comp Zero Period Do Nothing Clear Low Set High Toggle SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 664: Action-Qualifier Event Priority For Up-Down-Count Mode
(TBCTR=CMPA or CMPB). If CMPA/CMPB > TBPRD, then the event will not occur. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 665 Compare when using Shadow to Active Load of Action Qualifier Output A/B Control Register on TBCTR = 0 boundary. SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 666: Aqctlr[Shdwaqamode]
TBCTL[SWFSYNC] AQCTLB(16) Active Reg AQCTLR AQCTLB(16) [LDAQBMODE] Shadow Reg AQCTLR[SHDWAQBMODE] CTR = PRD CTR = Zero C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 667 TBPRD-1. This means there will always be a pulse of at least one TBCLK cycle in a PWM period which, when very short, tend to be ignored by the system. SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 668: Up-Down-Count Mode Symmetrical Waveform
Up-Down means Count-up-and-down mode, Up means up-count mode and Dwn means down-count mode • Sym = Symmetric, Asym = Asymmetric C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 669: Up, Single Edge Asymmetric Waveform, With Independent Modulation On Epwmxa And Epwmxb-Active High
// = = = = = = = = = = = = = = = = = = = = = = = = EPwm1Regs.CMPA.half.CMPA = Duty1A; // adjust duty for output EPWM1A SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 670: Up, Single Edge Asymmetric Waveform With Independent Modulation On Epwmxa And Epwmxb-Active Low
Example 7-2 contains a code sample showing initialization and run time for the waveforms in Figure 7-25. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 671: Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation On Epwmxa
Figure 7-26. Use the code in Example 7-5 to define the headers. SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 672 // = = = = = = = = = = = = = = = = = = = = = = = = EPwm1Regs.CMPA.half.CMPA = EdgePosA; // adjust duty for output EPWM1A only EPwm1Regs.CMPB = EdgePosB; C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 673: Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation On Epwmxa And Epwmxb - Active Low
EPwm1Regs.CMPA.half.CMPA = Duty1A; // adjust duty for output EPWM1A EPwm1Regs.CMPB = Duty1B; // adjust duty for output EPWM1B SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 674: Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation On Epwmxa And Epwmxb - Complementary
EPwm1Regs.CMPA.half.CMPA = Duty1A; // adjust duty for output EPWM1A EPwm1Regs.CMPB = Duty1B; // adjust duty for output EPWM1B C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 675: Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation On Epwmxa-Active Low
// = = = = = = = = = = = = = = = = = = = = = = = = EPwm1Regs.CMPA.half.CMPA = EdgePosA; // adjust duty for output EPWM1A only EPwm1Regs.CMPB = EdgePosB; SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 676: Dead_Band Submodule
The following list shows the distinct difference between type 1 and type 2 modules with respect to Dead Band operating modes C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 677 Controlling and Monitoring the Dead-Band Submodule The dead-band submodule operation is controlled and monitored via the following registers: SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 678: Dead-Band Generator Submodule Registers
C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 679: Configuration Options For The Dead-Band Submodule
EPWMxA and EPWMxB Passed Through (No Delay) Active High Complementary (AHC) Active Low Complementary (ALC) Active High (AH) Active Low (AL) SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 680: Additional Dead-Band Operating Modes
When this bit is set to 1, user should always either set OUT_MODE bits such that Apath = InA or OUTSWAP bits such that EPWMxA=Bpath. Otherwise, EPWMxA will be invalid. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 681: Dead-Band Waveforms For Typical Cases (0% < Duty < 100%)
Delayed (FED) Active High Complementary (AHC) Active Low Complementary (ALC) Active High (AH) Active Low (AL) SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 682: Dead-Band Delay Values In Μs As A Function Of Dbfed And Dbred
When half-cycle clocking is enabled, the formula to calculate the falling-edge-delay and rising-edge-delay becomes: FED = DBFED × T TBCLK RED = DBRED × T TBCLK C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 683: Pwm-Chopper Submodule
The one-shot width is programmed via the OSHTWTH bits. The PWM-chopper submodule can be fully disabled (bypassed) via the CHPEN bit. SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 684: Pwm-Chopper Submodule Operational Details
Details of the one-shot and duty-cycle control are discussed in the following sections. Figure 7-35. Simple PWM-Chopper Submodule Waveforms Showing Chopping Action Only EPWMxA EPWMxB PSCLK EPWMxA EPWMxB C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 685: Pwm-Chopper Submodule Waveforms Showing The First Pulse And Subsequent Sustaining Pulses
SYSCLKOUT = 80 MHz OSHTWTHz Pulse Width (hex) (nS) 1000 1100 1200 1300 1400 1500 1600 SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 686: Pwm-Chopper Submodule Waveforms Showing The Pulse Width (Duty Cycle) Control Of Sustaining Pulses
PSCLK PSCLK period PSCLK Period 62.5% 87.5% 37.5% 12.5% Duty Duty Duty Duty Duty Duty Duty C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 687: Trip-Zone Submodule
Software-forced tripping is also supported. • The trip-zone submodule can be fully bypassed if it is not required. SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 688: Trip-Zone Submodule Registers
When a one-shot trip event occurs, the action specified in the TZCTL[TZA] and TZCTL[TZB] bits is C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 689 TZCTL register bit fields. One of four possible actions, shown in Table 7-21, can be taken on a trip event. SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 690: Possible Actions On A Trip Event
DCAEVT1/2 and DCBEVT1/2 signals are described in further detail in Section 7.2.9. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 691: Trip-Zone Submodule Mode Control Logic
Async Sync Clear Trip TZFLG[OST] DCAEVT1.force DCBEVT1.force One-Shot (OSHT) Trip Events TZSEL[OSHT1 to OSHT6, DCAEVT1, DCBEVT1] SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 692: Trip-Zone Submodule Interrupt Logic
ADC when a selected event occurs. Figure 7-41 illustrates where the event-trigger submodule fits within the ePWM system. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 693: Event-Trigger Submodule
00111 EPWM1SYNC 01000 EPWM2SOCA EPWM2 01001 EPWM2SOCB 01010 EPWM2SYNC 01011 EPWM3SOCA EPWM3 01100 EPWM3SOCB 01101 EPWM3SYNC SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 694: Event-Trigger Submodule Inter-Connectivity Of Adc Start Of Conversion
ADC start of conversion. The event-trigger prescaling logic can issue Interrupt requests and ADC start of conversion at: • Every event • Every second event • Up to Every fifteenth event C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 695: Event-Trigger Submodule Showing Event Inputs And Prescaled Outputs
ETCNTINIT - These bits allow you to initialize INT/SOCA/SOCB counters on SYNC events (or software force) with user programmed value. SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 696 Writing an INTPRD value that is LESS than the current counter value will result in undefined behavior (that is, INTCNT stops counting because INTPRD is below INTCNT, and interrupt will never fire). C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 697: Event-Trigger Interrupt Generator
(DC) submodule. The SOCACNT2 initialization scheme is very similar to the interrupt generator with respective enable, value initialize and SYNC or software force options. SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 698: Event-Trigger Soca Pulse Generator
ETSEL[SOCBSELCMP] The DCBEVT1.soc signals are signals generated by the Digital compare (DC) submodule in Section 7.2.9. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 699: Digital-Compare Submodule High-Level Block Diagram
[DCAHTRIPSEL, DCALTRIPSEL, DCBHTRIPSEL, DCBLTRIPSEL] The ECAP input signals are sourced from the GPTRIP signals as shown in Figure 7-48. SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 700: Gpio Mux-To-Trip Input Connectivity
DCAH/L and DCBH/L signals trigger events which can then either be filtered or fed directly to the trip- C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 701: Digital Compare Submodule Registers
The TZDCSEL register is part of the trip-zone submodule but is mentioned again here because of its functional significance to the digital compare submodule. SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 702 The diagrams below show how the DCAEVT1, DCAEVT2 or DCEVTFLT signals are processed to generate the digital compare A event force, interrupt, soc and sync signals. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 703: Dcaevt1 Event Triggering
Figure 7-50. DCAEVT2 Event Triggering DCACTL[EVT2SRCSEL] DCACTL[EVT2FRCSYNCSEL] DCEVTFILT Async DCAEVT2 DCAEVT2.force Sync TZEINT[DCAEVT2] TBCLK TZFRC[DCAEVT2] Latch DCAEVT2.inter Clear TZFLG[DCAEVT2] TZCLR[DCAEVT2] SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 704: Dcbevt1 Event Triggering
ADC start-of-conversion. The event filtering can also capture the TBCTR value of the trip event. The diagram below shows the details of the event filtering logic. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 705: Event Filtering
CTR = 0 or CTR = PRD pulse. SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 706: Blanking Window Timing Diagram
CTR = 0 Offset(n) Offset(n+1) BLANKWDW Window(n) Window(n+1) Offset(n) Offset(n+1) BLANKWDW Window(n) Window(n+1) Offset(n) Offset(n+1) BLANKWDW Window(n+1) Window(n) C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 707: Simplified Epwm Module
SyncIn strobe input or choose to ignore it, i.e., via the enable switch. Although various combinations are possible, the two most common—master module and slave module modes—are shown in Figure 7-56. SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 708: Epwm1 Configured As A Typical Master, Epwm2 Configured As A Slave
Figure 7-57; note that only three waveforms are shown, although there are four stages. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 709: Control Of Four Buck Stages. Here F
EPWM4A CTR=CMPB SyncOut NOTE: Θ = X indicates value in phase register is a "don't care" SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 710: Buck Waveforms For (Note: Only Three Bucks Shown Here)
EPWM3A Indicates this event triggers an ADC start Indicates this event triggers an interrupt of conversion C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 711 EPwm2Regs.CMPA.half.CMPA = 700; // adjust duty for output EPWM2A EPwm3Regs.CMPA.half.CMPA = 500; // adjust duty for output EPWM3A SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 712: Control Of Four Buck Stages
Slave EPWM2A Phase reg SyncIn Φ=X EPWM2A Vin4 Vout4 EPWM2B CTR=zero CTR=CMPB Buck #4 SyncOut EPWM2B C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 713: Pwm1) )
Figure 7-60. Buck Waveforms for Figure 7-59 (Note: F PWM2 PWM1) EPWM1A EPWM1B EPWM2A EPWM2B SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 714 EPwm2Regs.CMPA.half.CMPA = 500; // adjust duty for output EPWM2A EPwm2Regs.CMPB = 300; // adjust duty for output EPWM2B C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 715 EPWM1B SyncOut Slave Phase reg SyncIn DC_bus Φ=0° EPWM2A out2 EPWM2B CTR=zero EPWM2A CTR=CMPB SyncOut EPWM2B SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 716 Figure 7-62. Half-H Bridge Waveforms for Figure 7-61 (Note: Here F PWM2 PWM1 EPWM1A EPWM1B Pulse Center EPWM2A EPWM2B Pulse Center C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 717 1, 2, 3 (also all equal). SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 718: Control Of Dual 3-Phase Inverter Stages As Is Commonly Used In Motor Control
3 phase motor SyncOut Slave Phase reg SyncIn 3 phase inverter #2 Φ=0° EPWM6A EPWM6B CTR=zero CTR=CMPB SyncOut C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 719: 3-Phase Inverter Waveforms For (Only One Inverter Shown)
Figure 7-64. 3-Phase Inverter Waveforms for Figure 7-63 (Only One Inverter Shown) EPWM1A EPWM1B Φ2=0 EPWM2A EPWM2B Φ3=0 EPWM3A EPWM3B SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 720 EPwm2Regs.CMPA.half.CMPA = 600; // adjust duty for output EPWM2A EPwm3Regs.CMPA.half.CMPA = 700; // adjust duty for output EPWM3A C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 721: Configuring Two Pwm Modules For Phase Control
SyncIn pulse (CTR = PRD), the value of TBPHS = 200 is loaded into the slave TBCTR register so the slave time-base is always leading the master's time-base by 120°. SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 722: Timing Waveforms Associated With Phase Control Between 2 Modules
TBPHS(3,3) = 400 (i.e., Phase value for Slave module 3) Figure 7-68 shows the waveforms for the configuration in Figure 7-67. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 723: Control Of A 3-Phase Interleaved Dc/Dc Converter
Φ=120° EPWM2A EPWM2B CTR=zero CTR=CMPB SyncOut Slave Phase reg SyncIn Φ=240° EPWM3A EPWM3B CTR=zero CTR=CMPB SyncOut SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 724: 3-Phase Interleaved Dc/Dc Converter Waveforms For
Figure 7-68. 3-Phase Interleaved DC/DC Converter Waveforms for Figure 7-67 EPWM1A EPWM1B Φ2=120° TBPHS (=300) EPWM2A EPWM2B Φ2=120° TBPHS (=300) EPWM3A EPWM3B C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 725 EPwm2Regs.CMPA.half.CMPA = 285; // adjust duty for output EPWM2A EPwm3Regs.CMPA.half.CMPA = 285; // adjust duty for output EPWM3A SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 726: Controlling A Full-H Bridge Stage
SyncOut Slave Phase reg SyncIn EPWM2A Φ=Var° EPWM1B EPWM2B EPWM2B CTR=zero CTR=CMPB SyncOut Var = Variable C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 727: Zvs Full-H Bridge Waveforms
1200 EPWM1A ZVS transition Power phase EPWM1B ZVS transition Φ2=variable TBPHS =(1200−Φ2) EPWM2A EPWM2B Power phase SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 728 10-bit DAC can be used to provide a reference peak current at the negative C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 729: Peak Current Mode Control Of A Buck Converter
Figure 7-71 ePWM1 TBPRD Time base = 300 Increased DAC OUT/ Load COMP1- Isense DCAEVT2.force ePWM1A SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 730 30 @100MHz TBCLK), it is up to user to update it in real time to enhance the efficiency by adjusting enough time delay for soft switching. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 731: Control Of Two Resonant Converter Stages
Indicates this event triggers an ADC Indicates this event triggers an interrupt start of conversion SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 732 EPwm1Regs.CMPA.half.CMPA= period_new value/2; // Update new CMPA EPwm1Regs.CMPB= period_new value/4; // Update new CMPB // Update new CMPB C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 733: Time-Base Period And Mirror 2 Register (Tbprd / Tbprdm2)
Figure 7-77. Time-Base Period Mirror Register (TBPRDM) TBPRD R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 734: Time-Base Period High-Resolution Mirror Register (Tbprdhrm)
Figure 7-79. Time-Base Phase Register and Mirror Register (TBPHS / TBPHSM) TBPHS R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 735: Time-Base Phase High-Resolution Register And Mirror Register (Tbphshr / Tbphshrm)
R/W-0 R/W-0 R/W-11 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 736: Time-Base Control Register (Tbctl) Field Descriptions
CTR = CMPB : Time-base counter equal to counter-compare B (TBCTR = CMPB) Disable EPWMxSYNCO signal C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 737 These bits set the time-base counter mode of operation as follows: Up-count mode Down-count mode Up-down-count mode Stop-freeze counter operation (default on reset) SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 738: Time-Base Status Register (Tbsts)
This register is EALLOW protected. This register is used with Type 1 ePWM modules (support high-resolution period) only. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 739: Time-Base Control Register 2 (Tbctl2)
R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 740: Epwmx Link Register (Epwmxlink) Field Descriptions
1010 ePWM9 All other values are reserved and do nothing (i.e., register is linked to itself). C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 741 1010 ePWM9 All other values are reserved and do nothing (i.e., register is linked to itself). SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 742: Counter-Compare Control Register (Cmpctl)
Immediate mode. Only the active compare register is used. All writes and reads directly access the active register for immediate compare action C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 743: Compare Control Register (Cmpctl2)
Immediate mode – only the Active compare register is used. All writes/reads via the CPU directly access the Active register for immediate “Compare action”. SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 744: Compare A High-Resolution And Mirror 2 Register (Cmpahr / Cmpahrm2 )
Shadowing is enabled and disabled by the CMPCTL[SHDWAMODE] bit as described for the CMPA register. Reserved Reserved for TI Test C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 745: Counter-Compare A And Mirror 2 Register (Cmpa / Cmpam2)
Figure 7-92. Counter-Compare A Mirror Register (CMPAM) CMPA R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 746: Counter-Compare B Register (Cmpbm)
Figure 7-94. Counter-Compare B Register (CMPB) CMPB R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 747: Counter-Compare C Register (Cmpc)
Figure 7-96. Counter-Compare D Register (CMPD) CMPD R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 748: Compare B High-Resolution Register (Cmpbhr)
By default writes to this register are shadowed. Shadowing is enabled and disabled by the CMPCTL[SHDWBMODE] bit as described for the CMPBM register. Reserved Reserved for TI test. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 749: Action-Qualifier Output A Control Register And Mirror Register (Aqctla / Aqctlam)
Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low. SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 750: Action-Qualifier Output B Control Register And Mirror Register (Aqctlb / Aqctlbm)
Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 751: Action-Qualifier Software Force Register And Mirror Register (Aqsfrc / Aqsfrcm)
Toggle (Low -> High, High -> Low) Note: This action is not qualified by counter direction (CNT_dir) SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 752: Action-Qualifier Continuous Software Force Register And Mirror Register (Aqcsfrc / Aqcsfrcm)
Forces a continuous low on output A Forces a continuous high on output A Software forcing is disabled and has no effect C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 753: Action Qualifier Control Register (Aqctlr)
Load on either CTR = Zero or CTR = PRD Freeze (no loads possible) Note: has no effect in Immediate mode. SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 754: Dead-Band Generator Control Register (Dbctl)
Shadow mode. Operates as a double buffer. All writes via the CPU access the Shadow register. Default at Reset is Immediate mode (for compatibility with legacy). C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 755 Bpath = InB (delay is by-passed for B signal path) DBM is fully enabled (i.e. both RED and FED active) SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 756: Dead-Band Generator Rising Edge Delay And Mirror Register (Dbred / Dbredm)
DBFEDHR Reserved R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 757: Dead Band Falling Edge Delay High-Resolution Register (Dbfedhr) Field Descriptions
DBCTL[SHDWDBFEDMODE] bit as described for the DBFED register. Reserved Reserved for TI Test SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 758: Pwm-Chopper Control Register (Pcctl)
15 x SYSCLKOUT / 8 wide ( = 1200 nS at 100 MHz SYSCLKOUT) 1111 16 x SYSCLKOUT / 8 wide ( = 1280 nS at 100 MHz SYSCLKOUT) C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 759 Table 7-59. PWM-Chopper Control Register (PCCTL) Bit Descriptions (continued) Field Value Description CHPEN PWM-chopping Enable Disable (bypass) PWM chopping function Enable chopping function SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 760: Trip-Zone Select Register (Tzsel)
Disable DCAEVT2 as a CBC trip source for this ePWM module Enable DCAEVT2 as a CBC trip source for this ePWM module C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 761: Trip-Zone Control Register (Tzctl)
Force EPWMxA to a high state. Force EPWMxA to a low state. Do Nothing, trip action is disabled SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 762: Trip-Zone Enable Interrupt Register (Tzeint)
Disable cycle-by-cycle interrupt generation. Enable interrupt generation; a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 763: Trip-Zone Flag Register (Tzflg)
Clearing all flag bits will prevent further interrupts. This bit is cleared by writing the appropriate value to the TZCLR register. SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 764: Trip-Zone Clear Register And Mirror Register (Tzclr / Tzclrm)
TZFLG[INT] bit is cleared and any of the other flag bits are set, then another interrupt pulse will be generated. Clearing all flag bits will prevent further interrupts. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 765: Trip-Zone Force Register (Tzfrc)
R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 766: Trip Zone Digital Compare Event Select Register (Tzdcsel) Field Descriptions
DCAL = low, DCAH = don't care DCAL = high, DCAH = don't care DCAL = high, DCAH = low reserved reserved C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 767: Digital Compare Trip Select (Dctripsel)
TRIPIN14 1110 TRIPIN15 1111 Trip combination input (all trip inputs selected by DCALTRIPSEL register ORed together) SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 768: Digital Compare A Control Register (Dcactl)
Source Is Asynchronous Signal EVT1SRCSEL DCAEVT1 Source Signal Select Source Is DCAEVT1 Signal Source Is DCEVTFILT Signal C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 769: Digital Compare B Control Register (Dcbctl)
15-13 Reserved Reserved 12-8 Reserved Reserved for TI Test Reserved Reserved Reserved Reserved for TI Test SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 770: Digital Compare Capture Control Register (Dccapctl)
Figure 7-122. Digital Compare Counter Capture Register (DCCAP) DCCAP LEGEND: R/W = Read/Write; R = Read only; -n = value after reset C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 771: Digital Compare Filter Offset Register (Dcfoffset)
The offset counter is not affected by the free/soft emulation bits. That is, it will always continue to count down if the device is halted by a emulation stop. SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 772: Digital Compare Filter Window Register (Dcfwindow)
R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 773: Digital Compare A High Trip Input Select (Dcahtripsel) Field Descriptions
Trip Input 1 not selected as combinational ORed input Trip Input 1 selected as combinational ORed input to DCAH mux SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 774: Digital Compare A Low Trip Input Select (Dcaltripsel) (Eallow-Protected)
Trip Input 3 not selected as combinational ORed input Trip Input 3 selected as combinational ORed input to DCAL mux C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 775: Digital Compare B High Trip Input Select (Dcbhtripsel) (Eallow-Protected)
Trip Input 6 not selected as combinational ORed input Trip Input 6 selected as combinational ORed input to DCBH mux SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 776: Digital Compare B Low Trip Input Select (Dcbltripsel) (Eallow-Protected)
Trip Input 9 not selected as combinational ORed input Trip Input 9 selected as combinational ORed input to DCBL mux C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 777 Trip Input 1 not selected as combinational ORed input Trip Input 1 selected as combinational ORed input to DCBL mux SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 778: Gpio Trip Input Select Register (Gptripxsel)
Reserved GPTRIPxSEL R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 779: Gpio Trip Input Select Register (Gptripxsel) Field Descriptions
000001 Select the GPIO1 ..111110 Select the GPIO62 111111 Select the GPIO63 SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 780: Event-Trigger Selection Register (Etsel)
Enable event: time-base counter equal to CMPB when the timer is decrementing or CMPD when the timer is decrementing (*) Event selected is determined by SOCASELCMP bit. Reserved Reserved C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 781: Event-Trigger Prescale Register (Etps)
R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 782: Event-Trigger Prescale Register (Etps) Field Descriptions
No events have occurred. 1 event has occurred. 2 events have occurred. 3 events have occurred. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 783: Event-Trigger Interrupt Pre-Scale Register (Etintps)
2 events 0011 3 events 0100 4 events ..1111 15 events SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 784: Event-Trigger Soc Pre-Scale Register (Etsocps)
Generate interrupt on SOCBCNT2 = 4 (fourth event) ..1111 Generate interrupt on SOCBCNT2 = 15 (fifteenth event) C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 785: Event-Trigger Flag Register (Etflg)
If an interrupt is pending, it will not be generated until after the ETFLG[INT] bit is cleared. Refer to Figure 7-44. SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 786: Event-Trigger Clear Register And Mirror Register (Etclr / Etclrm)
Generates an interrupt on EPWMxINT and set the INT flag bit. This bit is used for test purposes. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 787: Event-Trigger Counter Initialization Control Register (Etcntinitctl)
INTINIT R/W-0:00 R/W-0:00 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 788: Event-Trigger Counter Initialization Register (Etcntinit) Field Descriptions
The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 789 6. Clear any spurious ePWM flags (including PIEIFR) 7. Enable ePWM interrupts 8. Enable global interrupts SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 790 Capture Module - Control and Status Registers ..................... Register Mapping ................ Application of the ECAP Module ................Application of the APWM Mode C28 Enhanced Capture (eCAP) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 791 Control for continuous time-stamp captures using a 4-deep circular buffer (CAP1-CAP4) scheme • Interrupt capabilities on any of the 4 capture events SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 792: Capture And Apwm Modes Of Operation
Figure 8-2 further descries the output of the eCAP in APWM mode based on the CMP and PRD values. C28 Enhanced Capture (eCAP) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 793: Counter Compare And Prd Effects On The Ecap Output In Apwm Mode
ECAPOUT Off−time Period time Capture Mode Description Figure 8-3 shows the various components that implement the capture function. SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 794: Capture Function Diagram
This is useful when very high frequency signals are used as inputs. Figure 8-4 shows a functional diagram and Figure 8-5 shows the operation of the prescale function. C28 Enhanced Capture (eCAP) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 795: Event Prescale Control
A 2-bit stop register is used to compare the Mod4 counter output, and when equal stops the Mod4 counter and inhibits further loads of the CAP1-CAP4 registers. This occurs during one-shot operation. SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 796: Details Of The Continuous/One-Shot Block
The 32-bit counter value is captured first, then it is reset to 0 by any of the LD1-LD4 signals. C28 Enhanced Capture (eCAP) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 797: Details Of The Counter And Synchronization Block
You can force an interrupt event via the interrupt force register (ECFRC). This is useful for test purposes. SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 798: Interrupts In Ecap Module
Immediate - APRD or ACMP are transferred to CAP1 or CAP2 immediately upon writing a new value. • On period equal, CTR[31:0] = PRD[31:0] C28 Enhanced Capture (eCAP) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 799: Pwm Waveform Details Of Apwm Mode Operation
CMP = PERIOD+1, output low for complete period (100% duty) CMP > PERIOD+1, output low for complete period SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 800: Time-Base Frequency And Period Calculation
Capture Mode Description www.ti.com Figure 8-10. Time-Base Frequency and Period Calculation CAP1 1 TSCTR C28 Enhanced Capture (eCAP) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 801: Time-Stamp Counter Register (Tsctr)
• Software - may be useful for test purposes • APRD shadow register (CAP4) when used in APWM mode SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 802: Capture-3 Register (Cap3)
Divide by 1 (i.e,. no prescale, by-pass the prescaler) 00001 Divide by 2 00010 Divide by 4 00011 Divide by 6 C28 Enhanced Capture (eCAP) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 803: Ecap Control Register 2 (Ecctl2)
R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 804: Ecap Control Register 2 (Ecctl2) Field Descriptions
Wrap after Capture Event 1 in continuous mode. Stop after Capture Event 2 in one-shot mode Wrap after Capture Event 2 in continuous mode. C28 Enhanced Capture (eCAP) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 805 Continuous or one-shot mode control (applicable only in capture mode) Operate in continuous mode Operate in one-Shot mode SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 806: Ecap Interrupt Enable Register (Eceint)
• Clear spurious eCAP interrupt flags • Enable eCAP interrupts • Start eCAP counter • Enable global interrupts C28 Enhanced Capture (eCAP) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 807: Ecap Interrupt Flag Register (Ecflg)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 808: Ecap Interrupt Forcing Register (Ecfrc)
Force Counter Equal Period Interrupt No effect. Always reads back a 0. Writing a 1 sets the CTR=PRD flag bit. C28 Enhanced Capture (eCAP) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 809: Control And Status Register Set
Below are useful #defines which will help in the understanding of the examples. // ECCTL1 (ECAP Control Reg 1) //========================== SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 810: Capture Sequence For Absolute Time-Stamp And Rising Edge Detect
CAP2 CAP3 CAP4 All capture values valid Polarity selection (can be read) at this time Capture registers [1−4] C28 Enhanced Capture (eCAP) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 811 // Calculate 1st period Period2 = TSt3-TSt2; // Calculate 2nd period Period3 = TSt4-TSt3; // Calculate 3rd period SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 812: Capture Sequence For Absolute Time-Stamp With Rising And Falling Edge Detect
CEVT1 CEVT3 CEVT1 CAPx pin FFFFFFFF CTR[0−31] 00000000 MOD4 CAP1 CAP2 CAP3 CAP4 Polarity selection Capture registers [1−4] C28 Enhanced Capture (eCAP) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 813 // Calculate 1st period DutyOnTime1 = TSt2-TSt1; // Calculate On time DutyOffTime1 = TSt3-TSt2; // Calculate Off time SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 814: Capture Sequence For Delta Mode Time-Stamp And Rising Edge Detect
CAP2 CAP3 CAP4 Polarity selection Capture registers [1−4] All capture values valid (can be read) at this time C28 Enhanced Capture (eCAP) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 815 // Fetch Time-Stamp captured at T2 Period2 = ECap1Regs.CAP3; // Fetch Time-Stamp captured at T3 Period3 = ECap1Regs.CAP4; // Fetch Time-Stamp captured at T4 SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 816: Capture Sequence For Delta Mode Time-Stamp With Rising And Falling Edge Detect
For subsequent compare updates, during run- time, only the shadow registers must be used. C28 Enhanced Capture (eCAP) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 817 // Fetch Time-Stamp captured at T4 DutyOffTime2 = ECap1Regs.CAP1; // Fetch Time- Stamp captured at T1 Period1 = DutyOnTime1 + DutyOffTime1; Period2 = DutyOnTime2 + DutyOffTime2; SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 818: Pwm Waveform Details Of Apwm Mode Operation
// Allow TSCTR to run // Run Time (Instant 1, for example, ISR call) //====================== ECap1Regs.CAP2 = 0x300; C28 Enhanced Capture (eCAP) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 819 // Run Time (Instant 2, for example, another ISR call) //======================\ ECap1Regs.CAP2 = 0x500; // Set Duty cycle, that is, compare value SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 820 Edge Capture Unit ....................eQEP Watchdog ....................Unit Timer Base ................... eQEP Interrupt Structure ....................eQEP Registers C28 Enhanced QEP (eQEP) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 821: Optical Encoder Disk
166.6 KHz, so by measuring the frequency of either the QEPA or QEPB output, the processor can determine the velocity of the motor. SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced QEP (eQEP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 822: Index Pulse Example
Unit time is basically the inverse of the velocity calculation rate. C28 Enhanced QEP (eQEP) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 823 This signal is typically connected to a sensor or limit switch to notify that the motor has reached a defined position. SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced QEP (eQEP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 824: Functional Block Diagram Of The Eqep Peripheral
0x04 0x00000000 eQEP Maximum Position Count QPOSCMP 0x06 0x00000000 eQEP Position-compare QPOSILAT 0x08 0x00000000 eQEP Index Position Latch C28 Enhanced QEP (eQEP) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 825 QCTMRLAT 0x1F 0x0000 eQEP Capture Timer Latch QCPRDLAT 0x20 0x0000 eQEP Capture Period Latch reserved 0x21 31/0 0x3F SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced QEP (eQEP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 826: Functional Block Diagram Of Decoder Unit
Clock and direction input to position counter is selected using QDECCTL[QSRC] bits, based on interface input requirement as follows: • Quadrature-count mode • Direction-count mode • UP-count mode • DOWN-count mode C28 Enhanced QEP (eQEP) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 827: Quadrature Decoder State Machine
(10) (01) Decrement Decrement counter counter QEPA QEPB Decrement Decrement counter counter eQEP signals Increment Increment counter counter SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced QEP (eQEP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 828: Quadrature-Clock And Direction Decoding
QEPB as a GPIO mux option, or ensure that a signal edge is not generated on the QEPB input. C28 Enhanced QEP (eQEP) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 829 (QEPSTS[FIDF]) in QEPSTS registers, it also remembers the quadrature edge on the first index marker so that same relative quadrature transition is used for index event reset operation. SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced QEP (eQEP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 830: Position Counter Reset By Index Pulse For 1000 Line Encoder (Qposmax = 3999 Or 0Xf9F)
9-9shows the position counter reset operation in this mode. The first index marker fields (QEPSTS[FIDF] and QEPSTS[FIMF]) are not applicable in this mode. C28 Enhanced QEP (eQEP) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 831: Position Counter Underflow/Overflow (Qposmax = 4)
The eQEP index and strobe input can be configured to latch the position counter (QPOSCNT) into QPOSILAT and QPOSSLAT, respectively, on occurrence of a definite event on these pins. SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced QEP (eQEP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 832: Software Index Marker For 1000-Line Encoder (Qepctl[Iel] = 1)
Figure 9-10. Software Index Marker for 1000-line Encoder (QEPCTL[IEL] = 1) QCLK QEPSTS:QDF QPOSCNT Index interrupt/ index event marker QPOSILAT QEPSTS:QDLF C28 Enhanced QEP (eQEP) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 833: Strobe Event Latch (Qepctl[Sel] = 1)
QEPCTL[SWI] bit. This bit is not automatically cleared. While the bit is still set, if a 1 is written to it again, the position counter will be re-initialized. SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced QEP (eQEP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 834: Eqep Position-Compare Unit
Position-Compare Control Register (QPOSCTL) and Table 9-5 describes the QPOSCTL bit fields. C28 Enhanced QEP (eQEP) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 835: Eqep Position-Compare Event Generation Points
( k ) + t ( k ) * t ( k * 1 ) where, SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced QEP (eQEP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 836 QPOSLAT, QCTMRLAT and QCPRDLAT registers, respectively, on unit time out. Figure 9-17 shows the capture unit operation along with the position counter. C28 Enhanced QEP (eQEP) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 837: Eqep Edge Capture Unit
Figure 9-16. Unit Position Event for Low Speed Measurement (QCAPCTL[UPPS] = 0010) QCLK UPEVNT X=N x P N - Number of quadrature periods selected using QCAPCTL[UPPS] bits SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced QEP (eQEP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 838: Eqep Edge Capture Unit - Timing Details
Unit time (T) and unit period(X) are configured using the QUPRD and QCAPCTL[UPPS] registers. Incremental position output and incremental time output is available in the QPOSLAT and QCPRDLAT registers. C28 Enhanced QEP (eQEP) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 839: Eqep Watchdog Timer
Section Section 9.5. Figure 9-19. eQEP Unit Time Base UTIME QEPCTL:UTE SYSCLKOUT QUTMR UTOUT QUPRD QFLG:UTO SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced QEP (eQEP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 840: Eqep Interrupt Generation
DOWN count mode for frequency measurement (QCLK = xCLK, QDIR = 0) SOEN Sync output-enable Disable position-compare sync output Enable position-compare sync output C28 Enhanced QEP (eQEP) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 841: Eqep Control (Qepctl) Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced QEP (eQEP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 842: Eqep Control (Qepctl) Register Field Descriptions
The position counter is latched to the QPOSILAT register and the direction flag is latched in the QEPSTS[QDLF] bit. This mode is useful for software index marking. C28 Enhanced QEP (eQEP) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 843: Eqep Position-Compare Control (Qposctl) Register
1 * 4 * SYSCLKOUT cycles 0x001 2 * 4 * SYSCLKOUT cycles 0xFFF 4096 * 4 * SYSCLKOUT cycles SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced QEP (eQEP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 844: Eqep Capture Control (Qcapctl) Register
Figure 9-26. eQEP Position Counter Initialization (QPOSINIT) Register QPOSINIT R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset C28 Enhanced QEP (eQEP) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 845: Eqep Maximum Position Count Register (Qposmax) Register
Figure 9-30. eQEP Strobe Position Latch (QPOSSLAT) Register QPOSSLAT LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced QEP (eQEP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 846: Eqep Position Counter Latch (Qposlat) Register
Figure 9-34. eQEP Watchdog Timer (QWDTMR) Register QWDTMR R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset C28 Enhanced QEP (eQEP) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 847: Eqep Watchdog Period (Qwdprd) Register
Interrupt is enabled Position-compare ready interrupt enable Interrupt is disabled Interrupt is enabled Position counter overflow interrupt enable SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced QEP (eQEP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 848: Eqep Interrupt Flag (Qflg) Register
No interrupt generated This bit is set after transferring the shadow register value to the active position compare register. C28 Enhanced QEP (eQEP) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 849: Eqep Interrupt Clear (Qclr) Register
No effect Clears the interrupt flag Clear eQEP compare match event interrupt flag No effect Clears the interrupt flag SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced QEP (eQEP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 850: Eqep Interrupt Force (Qfrc) Register
Force index event latch interrupt No effect Force the interrupt Force strobe event latch interrupt No effect Force the interrupt C28 Enhanced QEP (eQEP) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 851: Eqep Status (Qepsts) Register
Counter-clockwise rotation (or reverse movement) on the first index event Clockwise rotation (or forward movement) on the first index event SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced QEP (eQEP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 852: Eqep Capture Timer (Qctmr) Register
Figure 9-43. eQEP Capture Timer Latch (QCTMRLAT) Register QCTMRLAT LEGEND: R/W = Read/Write; R = Read only; -n = value after reset C28 Enhanced QEP (eQEP) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 853: Eqep Capture Period Latch (Qcprdlat) Register
SPRUH22I – April 2012 – Revised November 2019 C28 Enhanced QEP (eQEP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 854 ..............10.2 Analog Common Interface Bus (ACIB) ..............10.3 Analog-to-Digital Converter (ADC) ..................... 10.4 Comparator Block ................10.5 Analog Subsystem Software Analog Subsystem SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 855: Analog Subsystem Block Diagram
A simplified model of the ACIB is shown in Figure 10-2 and the signals are defined in Table 10-1. SPRUH22I – April 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 856: Simplified Acib Model
ADC trigger and interrupt signals in case of contention. For instances where operations are pending from multiple CPU or DMA sources, the transactions are processed in a round- robin manner. Analog Subsystem SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 857: 16-Bit Write
Addr Word Word Bus[7:0] Ready 2-3 Cycle Sync Stall Read Stall Sync Stall Ready 15:8 15:8 Size Digital Buffer Analog Buffer SPRUH22I – April 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 858: 32-Bit Read
Analog Buffer Figure 10-8. ADC Trigger Clock Trig Sync Ready 2-3 Cycle Sync Stall Ready Bus[7:0] Stall Size Digital Buffer Analog Buffer Analog Subsystem SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 859: Adc Interrupt
8 flexible PIE interrupts total for both ADC modules, can configure interrupt request after any conversion • 8 flexible NVIC interrupts total for both ADC modules, can configure interrupt request after any conversion SPRUH22I – April 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 860: Adc Module Block Diagram
The channel and sample window size for SOCx are configured with the CHSEL and ACQPS fields of the ADCSOCxCTL register. Analog Subsystem SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 861: Soc Block Diagram
// (ACQPS=6, CHSEL=1, TRIGSEL=5) ADCSOC2CTL = 2846h; // (ACQPS=6, CHSEL=1, TRIGSEL=5) ADCSOC3CTL = 2846h; // (ACQPS=6, CHSEL=1, TRIGSEL=5) TRIG1SEL = 000Bh // (TRIG1SEL=11) SPRUH22I – April 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 862: Trigxsel Trigger Options
10001 EPWM5SOCA EPWM5 10010 EPWM5SOCB 10011 EPWM5SYNC 10100 EPWM6SOCA EPWM6 10101 EPWM6SOCB 10110 EPWM6SYNC 10111 EPWM7SOCA EPWM7 11000 EPWM7SOCB 11001 EPWM7SYNC Analog Subsystem SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 863: Adcinx Input Model
Switch Resistance (R ): 3.4 k Ω Sampling Capacitor (C ): 1.6 pF Parasitic Capacitance (C ): 5 pF Ω Source Resistance (R ): 50 SPRUH22I – April 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 864: Oneshot Single Conversion
2 from the current RR pointer. This is because simultaneous mode will create result for SOCx and SOCx+1, and SOCx+1 will never be triggered by the user. Analog Subsystem SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 865 ADCCTL1.RESET bit is set, or when the SOCPRICTL register is written. An example of the round robin priority method is given in Figure 10-14. SPRUH22I – April 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 866: Round Robin Priority Example
If two high priority SOC’s are triggered at the same time, the SOC with the lower number will take precedence. Analog Subsystem SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 867: High Priority Example
High Priority RRPOINTER RRPOINTER (value = 7) (value = 7) High Priority High Priority RRPOINTER RRPOINTER (value = 7) (value = 12) SPRUH22I – April 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 868 There are a total of 8 interrupts available for both ADC1 and ADC2. Each ADC does not have its own set of 8 interrupts. These resources must be shared. Analog Subsystem SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 869: Interrupt Structure
NOTE: If the system is reset or the ADC module is reset using Bit 15 (RESET) from the ADC Control Register 1, the Device_cal() routine must be repeated. SPRUH22I – April 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 870 Texas Instruments cannot guarantee the parameters specified in the datasheet if a value other than the factory settings contained in the TI reserved OTP memory is written into the ADC trim registers.
Page 871 Digital Value = 4096 [(Input – VREFLO)/(VREFHI – VREFLO)] when VREFLO < Input < VREFHI Digital Value = 4095, when Input ≥ VREFHI *All fractional values are truncated SPRUH22I – April 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 872: Adc Registers
The base address of the ADCRESULT registers differs from the base address of the other ADC registers. In the header files, the ADCRESULT registers are found in the AdcResult register file, not AdcRegs. Analog Subsystem SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 873: Adc Control Register 1 (Adcctl1) (Address Offset 00H)
Simultaneous Mode: Cleared 14 ADC clocks after negative edge of S/H pulse ADC is available to sample next channel ADC is busy and cannot sample another channel SPRUH22I – April 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 874 VREFLO internally connected to the ADC for sampling Reserved Reserved 10.3.11.2 ADC Control Register 2 (ADCCTL2) The register and description are shown below. Analog Subsystem SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 875: Adc Control Register 2 (Adcctl2) (Address Offset 01H)
ADCINTFLG flag is set. Both ADCINTFLG and ADCINTOVF flags must be cleared before normal interrupt operation can resume. SPRUH22I – April 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 876: Adc Interrupt Flag Clear Register (Adcintflgclr) (Address Offset 05H)
LEGEND: R/W = Read/Write; R = Read only; R-0/W-1 =always read 0, write 1 to set; -n = value after reset Analog Subsystem SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 877: Interrupt Select 1 And 2 Register (Intsel1N2) (Address Offset 08H)
R/W-0 Reserved INT7CONT INT7E INT7SEL R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 878: Interrupt Select 9 And 10 Register (Intsel9N10) (Address Offset 0Ch)
ADCINTx pulses are generated whenever an EOC pulse is generated irrespective if the flag bit is cleared or not. INTxE ADCINTx Interrupt Enable ADCINTx is disabled. ADCINTx is enabled . Analog Subsystem SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 879: Adc Start Of Conversion Priority Control Register (Socprictl)
Table 10-13. SOCPRICTL Register Field Descriptions Field Value Description ONESHOT One shot mode disabled One shot mode enabled 14-11 Reserved Reserved SPRUH22I – April 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 880 SOC0-SOC14 are high priority, SOC15 is in round robin mode. All SOCs are in high priority mode, arbitrated by SOC number Others Invalid selection. Analog Subsystem SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 881: Adc Sample Mode Register (Adcsamplemode) (Address Offset 12H)
EOC8 and EOC9 associated with SOC8 and SOC9 pair. SOC8’s and SOC9’s results will be placed in ADCRESULT8 and ADCRESULT9 registers, respectively. SPRUH22I – April 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 882: Adc Interrupt Trigger Soc Select 1 Register (Adcintsocsel1) (Address Offset 14H)
No ADCINT will trigger SOCx. TRIGSEL field determines SOCx trigger. ADCINT1 will trigger SOCx. TRIGSEL field is ignored. ADCINT2 will trigger SOCx. TRIGSEL field is ignored. Invalid selection. Analog Subsystem SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 883: Adc Interrupt Trigger Soc Select 2 Register (Adcintsocsel2) (Address Offset 15H)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 884: Adc Soc Overflow 1 Register (Adcsocovf1) (Address Offset 1Ch)
ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set. NOTE: The following ADC SOC0 - SOC15 Control Registers are EALLOW protected. Analog Subsystem SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 885: Adc Soc0 - Soc15 Control Registers (Adcsocxctl) (Address Offset 20H - 2Fh)
ADCTRIG5 – ADC Trigger 5 ADCTRIG6 – ADC Trigger 6 ADCTRIG7 – ADC Trigger 7 ADCTRIG8 – ADC Trigger 8 Others Invalid selection. Reserved Reserved SPRUH22I – April 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 886 ADCINA5/ADCINB5 pair ADCINA6/ADCINB6 pair ADCINA7/ADCINB7 pair Invalid selection. Invalid selection. Invalid selection. Invalid selection. Invalid selection. Invalid selection. Invalid selection. Invalid selection. Analog Subsystem SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 887: Adc Reference/Gain Trim Register (Adcreftrim) (Address Offset 40H)
Figure 10-38. ADC Offset Trim Register (ADCOFFTRIM) (Address Offset 41h) Reserved OFFTRIM R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 888: Adc Revision Register (Adcrev) (Address Offset 4Fh)
SOC4, the completed results of those conversions will be placed in ADCRESULT4 and ADCRESULT5. See 1.11 for timings of when this register is written. Analog Subsystem SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 889: Analog Subsystem Control Registers (Analogsysctrlreg)
ADC Trigger Overflow Detect TRIGOVFCLR ADC Trigger Overflow Clear TRIG1SEL-TRIG8SEL 70h - 77h ADC Trigger 1-8 Input Select This register is EALLOW protected. SPRUH22I – April 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 890: Adc Interrupt Overflow Detect Register (Intovf)
No overflow. Overflow detected. ADCINT2 ADCINT2 Overflow Flag Status No overflow. Overflow detected. ADCINT1 ADCINT1 Overflow Flag Status No overflow. Overflow detected. Analog Subsystem SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 891: Adc Interrupt Overflow Clear Register (Intovfclr)
Clears overflow flag. ADCINT2 ADCINT2 Overflow Flag Clear No action. Clears overflow flag. ADCINT1 ADCINT1 Overflow Flag Clear No action. Clears overflow flag. SPRUH22I – April 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 892: Control System: Lock Register (Clock)
This bit, if written simultaneously with the correct PSWD value, will enable write protection for the CLKDIV bits in the CCLKCTL register. Write protection can only be disabled by a system reset. Reserved Reserved Analog Subsystem SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 893: Control System: Acib Status Register (Ccibstatus)
Reads of this bit will give the current state of the READY signal. APGOODSTS Analog Subsystem Power Good Status Power not present Power present SPRUH22I – April 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 894: Control System: Clock Control Register (Cclkctl)
Clock is turned off. Divide by /1 mode Divide by /2 mode Divide by /4 mode Divide by /8 mode (Default) Reserved Reserved Reserved Analog Subsystem SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 895: Adc Start Of Conversion Trigger Overflow Detect Register (Trigovf)
Indicates if overflow occurred on respective ADC trigger. No overflow. Overflow detected. TRIG1 Indicates if overflow occurred on respective ADC trigger. No overflow. Overflow detected. SPRUH22I – April 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 896: Adc Start Of Conversion Trigger Overflow Flag Clear Register (Trigovfclr)
Clears ADC trigger overflow flag in TRIGOVF register. No action. Clears overflow flag. TRIG1 Clears ADC trigger overflow flag in TRIGOVF register. No action. Clears overflow flag. Analog Subsystem SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 897: Adc Start Of Conversion Trigx Input Select Register (Trigxsel)
11001 EPWM7SYNC (EPWM7) 11010 EPWM8SOCA (EPWM8) 11011 EPWM8SOCB (EPWM8) 11100 EPWM8SYNC (EPWM8) 11101 EPWM9SOCA (EPWM9) 11110 EPWM9SOCB (EPWM9) 11111 EPWM9SYNC (EPWM9) SPRUH22I – April 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 898: Timing Example For Sequential Mode / Late Interrupt Pulse
Result 0 latched on this cycle does not include the additional cycles required for the C28x and M3 subsystems to read the ADC result registers using the ACIB. Analog Subsystem SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 899: Timing Example For Sequential Mode / Early Interrupt Pulse
Result 0 latched on this cycle does not include the additional cycles required for the C28x and M3 subsystems to read the ADC result registers using the ACIB. SPRUH22I – April 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 900: Timing Example For Simultaneous Mode / Late Interrupt Pulse
Result 0 (A) and Result 0 (B) latched on their respective cycles does not include the additional cycles required for the C28x and M3 subsystems to read the ADC result registers using the ACIB. Analog Subsystem SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 901: Timing Example For Simultaneous Mode / Early Interrupt Pulse
The comparator output can be externally connected to a GPIO in order to connect to an ePWM Trip Zone module. SPRUH22I – April 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 902: Comparator Block Diagram
(B side input) of the comparator. The voltage output of the DAC is controlled by the DACVAL bit field in the DACVAL register. The output of the DAC is given by the equation: Analog Subsystem SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 903 QUALSEL bit field. NOTE: Some downstream modules (such as the ePWM DC Submodule) may require a minimum comparator output pulse-width for correct operation. SPRUH22I – April 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 904: Comparator Control (Compctl) Register
Synchronization select for output of the comparator before being passed to ETPWM/GPIO blocks Asynchronous version of Comparator output is passed Synchronous version of comparator output is passed Analog Subsystem SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 905: Compare Output Status (Compsts) Register
Field Value Description 15-10 Reserved Reserved DACVAL 0-3FFh DAC Value bits, scales the output of the DAC from 0 – 1023. SPRUH22I – April 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 906: Dac Test (Dactest) Register
NOTE: The maximum clock frequency for the Analog Subsystem clock is 37.5 MHz. This function is successful if it returns a value of 0xA005. Analog Subsystem SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 907 2 registers. These are the registers written to using the AnalogClockEnable and AnalogClockDisable functions. Valid #define values for the AnalogConfigReg parameter are located in the F28M35x_AnalogSysCtrl_defines.h file. SPRUH22I – April 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 908 Choose Analog Config Register 2 (used to enable ADC2, COMP1,2,3,4,5,6) Valid #define values for the AnalogClockMask parameter are located in the sysctl.h file. Analog Subsystem SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 909 ADC1, ADC2, COMP1, and COMP4 analog peripherals. The example also reads the status of the Analog Subsystem Config Registers to check for correctness. SPRUH22I – April 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 910 Config 1 and Analog Config 2 Registers if the header file functions (InitSysCtrl, InitAdc1, and InitAdc2) are not used to enable ADC1 or ADC2. Analog Subsystem SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 911 Channel Priority ..............11.6 Address Pointer and Transfer Control ................. 11.7 Overrun Detection Feature ..................11.8 Register Descriptions SPRUH22I – April 2012 – Revised November 2019 C28 Direct Memory Access (DMA) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 912 Throughput: 4 cycles/word (5 cycles/word for McBSP reads) 11.2 Architecture 11.2.1 Block Diagram Figure 11-1 shows a device-level block diagram of the DMA. C28 Direct Memory Access (DMA) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 913: Dma Block Diagram
CONTROL.CHx[PERINTFRC] bit. Likewise, software can always clear a pending DMA trigger using the CONTROL.CHx[PERINTCLR] bit. SPRUH22I – April 2012 – Revised November 2019 C28 Direct Memory Access (DMA) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 914: Peripheral Interrupt Trigger Input Diagram
Table 11-1 shows the interrupt trigger source options that are available for each channel. C28 Direct Memory Access (DMA) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 915: Peripheral Interrupt Trigger Source Options
ADC 2 memory-mapped result registers • McBSP data receive registers (DRR2/DRR1) and data transmit registers (DXR2/DXR1) • ePWM1-9/HRPWM1-8 registers SPRUH22I – April 2012 – Revised November 2019 C28 Direct Memory Access (DMA) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 916: 4-Stage Pipeline Dma Transfer
If instead the channel were configured to transfer the same amount of data 32 bits at a time (the word size is configured to 32 bits) the transfer would take: C28 Direct Memory Access (DMA) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 917 DMA access to that same interface has priority over the pending CPU access when the current CPU access completes. SPRUH22I – April 2012 – Revised November 2019 C28 Direct Memory Access (DMA) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 918: Arbitration When Accessing Acib
In this mode, all channels have equal priority and each enabled channel is serviced in round-robin fashion as follows: C28 Direct Memory Access (DMA) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 919 Typically Channel 1 would be used in this mode for the ADC, since its data rate is so high. However, Channel 1 High Priority Mode may be used in conjunction with any peripheral. SPRUH22I – April 2012 – Revised November 2019 C28 Direct Memory Access (DMA) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 920 Source/Destination Begin Address Pointers (SRC/DST_BEG_ADDR)— This is the wrap pointer. C28 Direct Memory Access (DMA) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 921 This value is a signed 2's compliment number so that the address pointer can be incremented or decremented as required. SPRUH22I – April 2012 – Revised November 2019 C28 Direct Memory Access (DMA) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 922 All of the above features and modes are shown in Figure 11-6. C28 Direct Memory Access (DMA) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 923: Dma State Diagram
Generate DMACHx interrupt CHINTMODE CONTINUOUS to CPU at end of == 1 == 1 transfer (if enabled) SPRUH22I – April 2012 – Revised November 2019 C28 Direct Memory Access (DMA) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 924 11-7. If the overrun interrupt is enabled then the channel interrupt will be generated to the PIE module. C28 Direct Memory Access (DMA) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 925: Overrun Detection Logic
CONTROL.CHx CONTROL.CHx [PERINTFLG] MODE.CHx [OVRFLG] [CHINTE] PERx_INT Latch CONTROL.CHx MODE.CHx [ERRCLR] [OVERNITE] SPRUH22I – April 2012 – Revised November 2019 C28 Direct Memory Access (DMA) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 926: Dma Register Summary
Shadow Destination Begin and Current Address Pointer Section Registers 11.8.21 All DMA register writes are EALLOW protected. C28 Direct Memory Access (DMA) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 927: Dma Control Register (Dmactrl)
In case CH1 is high priority, the state machine restarts from CH2 (or the next highest enabled channel). SPRUH22I – April 2012 – Revised November 2019 C28 Direct Memory Access (DMA) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 928 (i.e., a NOP instruction) after writing to this bit should be introduced before attempting an access to any other DMA register. C28 Direct Memory Access (DMA) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 929: Debug Control Register (Debugctrl)
DMA Silicon Revision Bits: These bits specify the DMA revision and are changed if any bug fixes are performed. 0x0000 First release SPRUH22I – April 2012 – Revised November 2019 C28 Direct Memory Access (DMA) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 930: Priority Control Register 1 (Priorityctrl1)
Channel priority can only be changed when all channels are disabled. A priority reset should be performed before restarting channels after changing priority. C28 Direct Memory Access (DMA) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 931: Priority Status Register (Prioritystat)
CH 1 0,1,0 CH 2 0,1,1 CH 3 1,0,0 CH 4 1,0,1 CH 5 1,1,0 CH 6 SPRUH22I – April 2012 – Revised November 2019 C28 Direct Memory Access (DMA) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 932: Mode Register (Mode)
The PERINTFLG being set indicates a previous peripheral event is latched and has not been serviced by the DMA. Reserved Reserved C28 Direct Memory Access (DMA) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 933 None ePWM5SOCA None ePWM5 ePWM5SOCB None ePWM6SOCA None ePWM6 ePWM6SOCB None ePWM7SOCA None ePWM7 ePWM7SOCB None SPRUH22I – April 2012 – Revised November 2019 C28 Direct Memory Access (DMA) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 934: Control Register (Control)
ADC or overrun has priority and the SYNCERR or OVRFLG bit is set. Reserved Reserved C28 Direct Memory Access (DMA) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 935 DMA channel out of a HALT condition See Figure 11-6 for the various positions the state machine can be at when HALTED. SPRUH22I – April 2012 – Revised November 2019 C28 Direct Memory Access (DMA) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 936: Burst Size Register (Burst_Size)
31 words left in a burst The above values represent the state of the counter at the HALT conditions. C28 Direct Memory Access (DMA) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 937: Source Burst Step Size Register (Src_Burst_Step)
Sub 2 from address 0xF000 Sub 4096 from address Only values from -4096 to 4095 are valid. SPRUH22I – April 2012 – Revised November 2019 C28 Direct Memory Access (DMA) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 938: Destination Burst Step Register Size (Dst_Burst_Step)
These bits specify the number of bursts to transfer: 0x0000 Transfer 1 burst 0x0001 Transfer 2 bursts 0x0002 Transfer 3 bursts 0xFFFF Transfer 65536 bursts C28 Direct Memory Access (DMA) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 939: Transfer Count Register (Transfer_Count)
Sub 2 from address 0xF000 Sub 4096 from address Only values from -4096 to 4095 are valid. SPRUH22I – April 2012 – Revised November 2019 C28 Direct Memory Access (DMA) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 940: Destination Transfer Step Size Register (Dst_Transfer_Step)
To disable the wrap function, set the WRAPSIZE bit field to a number larger than the TRANSFERSIZE bit field. C28 Direct Memory Access (DMA) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 941: Source/Destination Wrap Count Register (Scr/Dst_Wrap_Count)
Sub 2 from address 0xF000 Sub 4096 from address Only values from -4096 to 4095 are valid. SPRUH22I – April 2012 – Revised November 2019 C28 Direct Memory Access (DMA) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 942: Shadow Source Begin And Current Address Pointer Registers (Src_Beg_Addr_Shadow/Dst_Beg_Addr_Shadow) - All Eallow Protected
Table 11-22. Active Source Begin and Current Address Pointer Registers (SRC_BEG_ADDR/DST_BEG_ADDR) Field Descriptions Field Value Description 31-22 Reserved Reserved 21-0 BEGADDR 22-bit address value C28 Direct Memory Access (DMA) Module SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 943: Shadow Destination Begin And Current Address Pointer Registers (Src_Addr_Shadow/Dst_Addr_Shadow) - All Eallow Protected
Table 11-24. Active Destination Begin and Current Address Pointer Registers (SRC_ADDR/DST_ADDR) Field Descriptions Field Value Description 31-22 Reserved Reserved 21-0 ADDR 22-bit address value SPRUH22I – April 2012 – Revised November 2019 C28 Direct Memory Access (DMA) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 944: C28 Serial Peripheral Interface (Spi)
Enhanced SPI Module Overview ............. 12.2 C28 SPI-A to M3 SSI3 Internal Loopback ................12.3 SPI Registers and Waveforms C28 Serial Peripheral Interface (SPI) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 945: Enhanced Spi Module Overview
Simultaneous receive and transmit operation (transmit function can be disabled in software) • Transmitter and receiver operations are accomplished through either interrupt- driven or polled algorithms. SPRUH22I – April 2012 – Revised November 2019 C28 Serial Peripheral Interface (SPI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 946: Spi Block Diagram
SPI in slave mode, showing the basic control blocks available on the SPI module. C28 Serial Peripheral Interface (SPI) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 947: Serial Peripheral Interface Module Block Diagram
LSPCLK SPICCR.6 SPICTL.3 SPICLK SPIBRR.6 − 0 SPISTE of a slave device is driven low by the master. SPRUH22I – April 2012 – Revised November 2019 C28 Serial Peripheral Interface (SPI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 948: Spi Module Signal Summary
SPICCR (SPI configuration control register). Contains control bits used for SPI configuration – SPI module software reset – SPICLK polarity selection – Four SPI character-length control bits C28 Serial Peripheral Interface (SPI) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 949: Spi Operation
The master can initiate data transfer at any time because it controls the SPICLK signal. The software, however, determines how the master detects when the slave is ready to broadcast data. SPRUH22I – April 2012 – Revised November 2019 C28 Serial Peripheral Interface (SPI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 950: Spi Master/Slave Connection
The transfer rate is defined by this clock. The SPICLK input frequency should be no greater than the LSPCLK frequency divided by 4. C28 Serial Peripheral Interface (SPI) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 951: Spi Interrupts
If the CPU does not read the character by the time the next complete character has been received, the new character is written into SPIRXBUF, and the RECEIVER OVERRUN Flag bit (SPISTS.7) is set. SPRUH22I – April 2012 – Revised November 2019 C28 Serial Peripheral Interface (SPI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 952 = 1 if SPISOMI data is high; x = 0 if SPISOMI data is low; master mode is assumed. C28 Serial Peripheral Interface (SPI) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 953 Rising Edge With Delay. The SPI transmits data one half-cycle ahead of the rising edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. SPRUH22I – April 2012 – Revised November 2019 C28 Serial Peripheral Interface (SPI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 954: Spiclk Signal Options
Figure 12-5. SPI: SPICLK-CLKOUT Characteristic When (BRR + 1) is Odd, BRR > 3, and CLOCK POLARITY = 1 2 cycles 3 cycles 2 cycles CLKOUT SPICLK C28 Serial Peripheral Interface (SPI) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 955 (CLOCK POLARITY = 0) or during the high pulse (CLOCK POLARITY = 1) of the SPICLK. Figure 12-6 is applicable for 8-bit word length transmissions. The figure is shown for illustrative purposes only. SPRUH22I – April 2012 – Revised November 2019 C28 Serial Peripheral Interface (SPI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 956: Spi Fifo Description
SPI will be disabled and this interrupt will service as SPI receive FIFO interrupt. 6. Buffers. Transmit and receive buffers are supplemented with two 4x16 FIFOs. The one-word transmit C28 Serial Peripheral Interface (SPI) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 957: Spi Fifo Interrupt Flags And Enable Logic Generation
SPIRXINT Transmit empty SPIINT SPIINTENA SPIRXINT In non FIFO mode, SPIRXINT is the same as the SPIINT interrupt. SPRUH22I – April 2012 – Revised November 2019 C28 Serial Peripheral Interface (SPI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 958: Spi 3-Wire Mode Description
Figure 12-8. SPI 3-wire Master Mode GPIO MUX SPI Module Data RX SPIDAT Free pin Data TX SPIMOMIx Talk SPICTL.1 C28 Serial Peripheral Interface (SPI) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 959: Spi 3-Wire Slave Mode
!=1) {} // Waits until data rx’d dummy = SpiaRegs.SPIRXBUF; // Clears junk data from itself // bc it rx’d same data tx’d SPRUH22I – April 2012 – Revised November 2019 C28 Serial Peripheral Interface (SPI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 960: Spi Steinv Bit In Digital Audio Transfers
SPI modules can be connected as shown in Figure 12-10. C28 Serial Peripheral Interface (SPI) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 961: C28 Spi-A To M3 Ssi3 Internal Loopback
M3 SSI3 and C28 SPI-A. The internal connection logic block handles the signal routing between the peripherals and the GPIO mux. SPRUH22I – April 2012 – Revised November 2019 C28 Serial Peripheral Interface (SPI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 962: Loopback Initialization And Configuration
3. Enable and configure the C28 SPI module as detailed in Section 12.1.5.4. To enable M3 SSI3 slave to C28 SPI-A master loopback mode, perform the following steps: C28 Serial Peripheral Interface (SPI) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 963 CPHA bits are different from the C28 CPOL and CPHA bits. Using incompatible configurations can cause data to be shifted by one bit. SPRUH22I – April 2012 – Revised November 2019 C28 Serial Peripheral Interface (SPI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 964: Spi Registers And Waveforms
Table 12-9 lists the character length selected by the bit values. C28 Serial Peripheral Interface (SPI) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 965: Spi Operation Control Register (Spictl) - Address 7041H
During reset initialization, the SPI is automatically configured as a network slave. SPI configured as a slave. SPI configured as a master. SPRUH22I – April 2012 – Revised November 2019 C28 Serial Peripheral Interface (SPI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 966: Spi Status Register (Spist) - Address 7042H
This will alleviate any possible doubt as to the source of the interrupt when the next byte is received. C28 Serial Peripheral Interface (SPI) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 967: Spi Baud Rate Register (Spibrr) - Address 7044H
(SPISTS.6). This is not a real register but a dummy address from which the contents of SPIRXBUF can be read by the emulator without clearing the SPI INT FLAG. SPRUH22I – April 2012 – Revised November 2019 C28 Serial Peripheral Interface (SPI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 968: Spi Emulation Buffer Register (Spirxemu) - Address 7046H
In master mode, if no transmission is currently active, writing to this register initiates a transmission in the same manner that writing to SPIDAT does. C28 Serial Peripheral Interface (SPI) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 969: Spi Serial Transmit Buffer Register (Spitxbuf) - Address 7048H
SPRUH22I – April 2012 – Revised November 2019 C28 Serial Peripheral Interface (SPI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 970: Spi Fifo Transmit (Spifftx) Register − Address 704Ah
R/W−1 R/W−1 R/W−1 R/W−1 R/W−1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset C28 Serial Peripheral Interface (SPI) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 971: Spi Fifo Control (Spiffct) Register − Address 704Ch
In the FIFO mode TXBUF should not be treated as one additional level of buffer. SPRUH22I – April 2012 – Revised November 2019 C28 Serial Peripheral Interface (SPI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 972: Spi Priority Control Register (Spipri) - Address 704Fh
SIISOMI pin becomes the SPISISO (slave receive and transmit) pin and SPISIMO is free for non-SPI use. C28 Serial Peripheral Interface (SPI) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 973: Spi Example Waveforms
Figure 12-25. CLOCK POLARITY = 0, CLOCK PHASE = 0 (All data transitions are during the rising edge, non-delayed clock. Inactive level is low.) Ch1 Period 200 ns SPICLK SPISIMO SPRUH22I – April 2012 – Revised November 2019 C28 Serial Peripheral Interface (SPI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 974: By Half Clock Cycle. Inactive Level Is Low.)
Figure 12-26. CLOCK POLARITY = 0, CLOCK PHASE = 1 (All data transitions are during the rising edge, but delayed by half clock cycle. Inactive level is low.) Ch1 Period 200 ns SPICLK SPISIMO C28 Serial Peripheral Interface (SPI) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 975: Clock Polarity = 1, Clock Phase
Figure 12-27. CLOCK POLARITY = 1, CLOCK PHASE = 0 (All data transitions are during the falling edge. Inactive level is high.) Ch1 Period 199 ns SPICLK SPISIMO SPRUH22I – April 2012 – Revised November 2019 C28 Serial Peripheral Interface (SPI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 976: Clock Polarity = 1, Clock Phase
Figure 12-28. CLOCK POLARITY = 1, CLOCK PHASE = 1 (All data transitions are during the falling edge, but delayed by half clock cycle. Inactive level is high.) Ch1 Period 200 ns SPICLK SPISIMO C28 Serial Peripheral Interface (SPI) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 977: Spiste Behavior In Master Mode (Master Lowers Spiste During The Entire 16 Bits Of Transmission.)
Figure 12-29. SPISTE Behavior in Master Mode (Master lowers SPISTE during the entire 16 bits of transmission.) Ch1 Period 200 ns SPICLK SPISTE SPRUH22I – April 2012 – Revised November 2019 C28 Serial Peripheral Interface (SPI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 978: Spiste Behavior In Slave Mode (Slave's Spiste Is Lowered During The Entire 16 Bits Of Transmission.)
Figure 12-30. SPISTE Behavior in Slave Mode (Slave’s SPISTE is lowered during the entire 16 bits of transmission.) Ch1 Period 398 ns SPISIMO SPISTE C28 Serial Peripheral Interface (SPI) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 979: C28 Serial Communications Interface (Sci)
13.1 Enhanced SCI Module Overview ............13.2 C28 SCI-A to M3 UART4 Internal Loopback ....................13.3 SCI Registers SPRUH22I – April 2012 – Revised November 2019 C28 Serial Communications Interface (SCI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 980: Enhanced Sci Module Overview
(7−0), and the upper byte (15−8) is read as zeros. Writing to the upper byte has no effect. Enhanced features: C28 Serial Communications Interface (SCI) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 981: Serial Communications Interface (Sci) Module Block Diagram
SCIRXST.4 − 2 SCIFFRX.15 RX Error FE OE RX Error RX ERR INT ENA SCI RX Interrupt select logic SCICTL1.6 SPRUH22I – April 2012 – Revised November 2019 C28 Serial Communications Interface (SCI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 982: Architecture
– SCIRXBUF — receiver data buffer register. Contains data to be read by the CPU. Data from a remote processor is loaded into register RXSHF and then into registers SCIRXBUF and SCIRXEMU C28 Serial Communications Interface (SCI) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 983: Sci Module Signal Summary
A character of data with its formatting information is called a frame and is shown in Figure 13-3. SPRUH22I – April 2012 – Revised November 2019 C28 Serial Communications Interface (SCI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 984: Typical Sci Data Frame Formats
13.1.1.6) adds an extra bit (that is, an address bit) into every byte to distinguish addresses from data. This mode is more efficient in handling many small blocks of data C28 Serial Communications Interface (SCI) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 985: Idle-Line Multiprocessor Communication Format
Step 5. If the CPU is not being addressed, the SLEEP bit remains set. This lets the CPU continue to execute its main program without being interrupted by the SCI port until the next detection of SPRUH22I – April 2012 – Revised November 2019 C28 Serial Communications Interface (SCI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 986: Double-Buffered Wut And Txshf
The address bit is set to 1 in the first frame of the block and to 0 in all other frames. The idle period timing is irrelevant (see Figure 13-6). C28 Serial Communications Interface (SCI) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 987: Address-Bit Multiprocessor Communication Format
SPRUH22I – April 2012 – Revised November 2019 C28 Serial Communications Interface (SCI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 988: Sci Asynchronous Communications Format
• Address-bit wake-up mode (address bit does not appear in idle-line mode) • Three bits per character C28 Serial Communications Interface (SCI) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 989: Sci Tx Signals In Communications Mode
CPU can write to SCITXBUF; this action sets the TXRDY flag bit (SCICTL2, bit 7) and initiates an interrupt. SPRUH22I – April 2012 – Revised November 2019 C28 Serial Communications Interface (SCI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 990: Asynchronous Baud Register Values For Common Sci Bit Rates
SCI module can transmit data in continuous mode with the FIFO words shifting out back to back. C28 Serial Communications Interface (SCI) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 991: Sci Fifo Interrupt Flags And Enable Logic
RXERR can be set by BRKDT, FE, OE, PE flags. In FIFO mode, BRKDT interrupt is only through RXERR flag SPRUH22I – April 2012 – Revised November 2019 C28 Serial Communications Interface (SCI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 992: C28 Sci-A To M3 Uart4 Internal Loopback
The C28 SCI-A peripheral can be internally connected to the M3 UART4 peripheral. External GPIO pins are not used when the loopback feature is enabled and can be used for other functions. C28 Serial Communications Interface (SCI) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 993: Loopback Initialization And Configuration
3. Enable and configure the C28 SCI-A module as described in Section 13.1. To disable loopback between the M3 and C28, set SERPLOOP[UART4TOSCIA] = 0. SPRUH22I – April 2012 – Revised November 2019 C28 Serial Communications Interface (SCI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 994: Sci Registers
SCIFFRX 0x0000-775B SCI-B FIFO Receive Register SCIFFCT 0x0000-775C SCI-B FIFO Control Register SCIPRI 0x0000-775F SCI-B Priority Control Register C28 Serial Communications Interface (SCI) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 995: Sci Communication Control Register (Sciccr)
The bit values and character lengths for SCI CHAR2-0 bits are as follows: SCI CHAR2−0 Bit Values (Binary) SCI CHAR2 SCI CHAR1 SCI CHAR0 Character Length (Bits) SPRUH22I – April 2012 – Revised November 2019 C28 Serial Communications Interface (SCI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 996: Sci Control Register 1 (Scictl1)
TXWAKE is not cleared by the SW RESET bit (SCICTL1, bit 5); it is cleared by a system reset or the transfer of TXWAKE to the WUT flag. C28 Serial Communications Interface (SCI) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 997 Prevent received characters from transfer into the SCIRXEMU and SCIRXBUF receiver buffers Send received characters to SCIRXEMU and SCIRXBUF SPRUH22I – April 2012 – Revised November 2019 C28 Serial Communications Interface (SCI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 998: Sci Baud-Select Registers (Scihbaud, Scilbaud)
Note that the above formulas are applicable only when 1 ≤ BRR ≤ 65535. If BRR = 0, then LSPCLK SCI Asynchronous Baud (10) Where: BRR = the 16-bit value (in decimal) in the baud-select registers. C28 Serial Communications Interface (SCI) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 999: Sci Control Register 2 (Scictl2)
RX ERROR RXRDY BRKDT RXWAKE Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH22I – April 2012 – Revised November 2019 C28 Serial Communications Interface (SCI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 1000: Sci Receiver Status Register (Scirxst) Field Descriptions
• An active SW RESET • A system reset Reserved Reads return zero; writes have no effect. 1000 C28 Serial Communications Interface (SCI) SPRUH22I – April 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...

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