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Register Descriptions
21.7.6 UART Fractional Baud-Rate Divisor Register (UARTFBRD), offset 0x028
The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared on
reset. When changing the UARTFBRD register, the new value does not take effect until
transmission/reception of the current character is complete. Any changes to the baud-rate divisor must be
followed by a write to the UARTLCRH register. See
Figure 21-13. UART Fractional Baud-Rate Divisor Register (UARTFBRD)
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 21-8. UART Fractional Baud-Rate Divisor (UARTFBRD) Register Field Descriptions
Bit
Field
31-6
Reserved
5-0
DIVFRAC
21.7.7 UART Line Control Register (UARTLCRH), offset 0x02C
The UARTLCRH register is the line control register. Serial parameters such as data length, parity, and
stop bit selection are implemented in this register.
When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register must also
be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH register.
31
15
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 21-9. UART Line Control Register (UARTLCRH) Field Descriptions
Bit
Field
31-8
Reserved
7
SPS
6-5
WLEN
4
FEN
1504
M3 Universal Asynchronous Receivers/Transmitters (UARTs)
Reserved
R-0
Value
Description
Reserved
Fractional Baud-Rate Divisor
Figure 21-14. UART Line Control Register (UARTLCRH)
R-0
Value
Description
Reserved
UART Stick Parity Select
When bits 1, 2, and 7 of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When
bits 1 and 7 are set and 2 is cleared, the parity bit is transmitted and checked as a 1.When this bit
is cleared, stick parity is disabled.
UART Word Length
The bits indicate the number of data bits transmitted or received in a frame as follows:
0x0
5 bits (default)
0x1
6 bits
0x2
7 bits
0x3
8 bits
UART Enable FIFOs
0
The FIFOs are disabled (Character mode). The FIFOs become 1-byte-deep holding registers.
1
The transmit and receive FIFObuffers are enabled (FIFOmode).
Copyright © 2012–2019, Texas Instruments Incorporated
Section 21.3.2
for configuration details.
Reserved
R-0
8
7
6
5
SPS
WLEN
R/W-0
R/W-0
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
6
5
DIVFRAC
R/W-0
4
3
2
1
FEN
STP2
EPS
PEN
R/W-0
R/W-0
R/W-0
R/W-0
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0
16
0
BRK
R/W-0
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