Uart Interrupt Mask (Uartim) Register; Uart Interrupt Mask (Uartim) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Register Descriptions
21.7.10 UART Interrupt Mask (UARTIM) Register, offset 0x038
The UARTIM register is the interrupt mask set/clear register.
On a read, this register gives the current value of the mask on the relevant interrupt. Setting a bit allows
the corresponding raw interrupt signal to be routed to the interrupt controller. Clearing a bit prevents the
raw interrupt signal from being sent to the interrupt controller.
31
23
15 14
LME5IM LME1IM
R/W-0 R/W-0
7 6
FEIM RTIM
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 21-12. UART Interrupt Mask (UARTIM) Register Field Descriptions
Bit Field
31-16 Reserved
15 LME5IM
14 LME1IM
13 LMSBIM
12-11 Reserved
10 OEIM
9 BEIM
8 PEIM
7 FEIM
6 RTIM
1508
M3 Universal Asynchronous Receivers/Transmitters (UARTs)
Figure 21-17. UART Interrupt Mask (UARTIM) Register
13 12
LMSBIM
R/W-0
5 4
TXIM RXIM
R/W-0 R/W-0
Value Description
Reserved
LIN Mode Edge 5 Interrupt Mask
0 The LME5RIS interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the LME5RIS bit in the UARTRIS register is set.
LIN Mode Edge 1 Interrupt Mask
0 The LME1RIS interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the LME1RIS bit in the UARTRIS register is set.
LIN Mode Sync Break Interrupt Mask
0 The LMSBRIS interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the LMSBRIS bit in the UARTRIS register is set.
Reserved
UART Overrun Error Interrupt Mask
0 The OERIS interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the OERIS bit in the UARTRIS register is set.
UART Break Error Interrupt Mask
0 The BERIS interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the BERIS bit in the UARTRIS register is set.
UART Parity Error Interrupt Mask
0 The PERIS interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the PERIS bit in the UARTRIS register is set.
UART Framing Error Interrupt Mask
0 The FERIS interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the FERIS bit in the UARTRIS register is set.
UART Receive Time-Out Interrupt Mask
0 The RTRIS interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the RTRIS bit in the UARTRIS register is set.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
Reserved
R-0
11 10
Reserved OEIM
R-0 R/W-0
3
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
24
16
9 8
BEIM PEIM
R/W-0 R/W-0
0
Reserved
R-0
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