Introduction; Block Diagram; Functional Description; Usb Block Diagram - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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18.1 Introduction

The USB controller operates as a full-speed or low-speed function controller during point-to-point
communications with USB Host, Device, or OTG functions.
The USB module has the following features:
• Complies with USB-IF certification standards
• USB 2.0 full-speed (12 Mbps) and low-speed (1.5 Mbps) operation
• Integrated PHY
• Four transfer types: Control, Interrupt, Bulk, and Isochronous
• 32 endpoints
– One dedicated control IN endpoint and one dedicated control OUT endpoint
– 15 configurable IN endpoints and 15 configurable OUT endpoints
• Four KB dedicated endpoint memory: one endpoint may be defined for double-buffered 1023-byte
isochronous packet size
• VBUS droop and valid ID detection and interrupt
• Efficient transfers using direct memory access controller (DMA)
– Separate channels for transmit and receive for up to three IN endpoints and three OUT endpoints
– Channel requests asserted when FIFO contains required amount of data

18.1.1 Block Diagram

USB PHY
USB FS/LS
PHY
USB DataLines
D+ andD-

18.2 Functional Description

The USB controller provides full OTG negotiation by supporting both the session request protocol (SRP)
and the host negotiation protocol (HNP). The session request protocol allows devices on the B side of a
cable to request the A side device turn on VBUS. The host negotiation protocol is used after the initial
session request protocol has powered the bus and provides a method to determine which end of the cable
will act as the Host controller. When the device is connected to non-OTG peripherals or devices, the
controller can detect which cable end was used and provides a register to indicate if the controller should
act as the Host or the Device controller. This indication and the mode of operation are handled
automatically by the USB controller. This auto-detection allows the system to use a single A/B connector
instead of having both A and B connectors in the system and supports full OTG negotiations with other
OTG devices.
SPRUHE8E – October 2012 – Revised November 2019
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Figure 18-1. USB Block Diagram
EP0 –31
Control
Combine
Endpoints
Packet
UTM
Synchronization Encode/Decode
Data Sync Packet Encode
HNP/SRP Packet Decode
Timers CRC Gen/Check
Copyright © 2012–2019, Texas Instruments Incorporated
Endpoint Control
Transmit
Receive
Host
Transaction
Scheduler
FIFO RAM
Controller
Rx Rx
Buff Buff
Tx Tx
Buff Buff
Cycle Control
M3 Universal Serial Bus (USB) Controller
Introduction
DMA
Requests
CPU Interface
Interrupt
Interrupts
Control
EP Reg.
Decoder
CPU Bus
Common
Regs
Cycle
Control
FIFO
Decoder
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