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Host Bus Mode
Additionally, the Host-Bus mode provides read and write wait states for the data portion to support
different classes of device. These wait states stretch the data period (hold the rising edge of data strobe)
and may be used in all four sub-modes. The wait states are set using the WRWS and RDWS bits in the
EPI Host-Bus n Configuration (EPIHBnCFGn) register. The WRWS and RDWS bits are enhanced with
more precision by WRWSM and RDWSM bits in the EPIHBnTIMEn registers. Note none of the wait state
configuration bits can be set concurrently with the BURST bit in the same EPIHBnCFGn register. See
Table 17-8
for programming information.
RDWS or WRWS Encoding in
EPIHBnCFGn Register
0x0
0x0
0x1
0x1
0x2
0x2
0x3
0x3
The CAPWIDTH bit in EPIHBnTIMEn registers controls the delay between Host-Bus transfers. When the
CSBAUD bit is set and multi-chip selects have been configured in the EPIHBnCFG2 registers, delay takes
an additional clock cycle to adjust the clock rate of different chip selects.
Word read and write transactions can be enhanced through the enabling of the BURST bit in the
EPIHB16CFGn registers.
17.7.3 Sub-Modes of Host Bus 8/16
The EPI controller supports four variants of the Host-Bus model using 8 or 16 bits of data in all four cases.
The four sub-modes are selected using the MODE bits in the EPIHBnCFG register, and are:
•
Address and data are muxed. This scheme is used by many 8051 devices, some Microchip PIC parts,
and some ATmega parts. When used for standard SRAMs, a latch must be used between the
microcontroller and the SRAM. This sub-mode is provided for compatibility with existing devices that
support data transfers without a latch (that is, CPLDs). In general, the de-muxed sub-mode should
normally be used. The ALE configuration should be used in this mode, as all Host-Bus accesses have
an address phase followed by a data phase. The ALE indicates to an external latch to capture the
address then hold until the data phase. The ALE configuration is controlled by configuring the CSCFG
and CSCFGEXT field to be 0x0 in the EPIHBnCFG2 register. The ALE can be enhanced to access two
or four external devices with four separate CS signals. By configuring the CSCFG field to be 0x3 and
the CSCFGEXT bit to be 0 in the EPIHBnCFG2 register, EPI0S30 functions as ALE, EPI0S27
functions as CS1, and EPI0S26 functions as CS0. When the CSCFG field is set to 0x0 and the
CSCFGEXT bit is set to 1 in the EPIHBnCFG2 register, EPI0S30 functions as ALE, EPIOS33 functions
as CS3, EPIOS34 functions as CS2, EPI0S27 functions as CS1, and EPI0S26 functions as CS0. The
CS is best used for host-bus unmuxed mode, in which EPI address and data pins are separate. The
CS indicates when the address and data phases of a read or write access are occurring.
•
Address and data are separate with 8 or 16 bits of data and up to 20 bits of address (1 MB). This
scheme is used by more modern 8051 devices, as well as some PIC and ATmega parts. This mode is
generally used with real SRAMs, many EEPROMs, and many NOR Flash memory devices. Note that
there is no hardware command write support for Flash memory devices; this mode should only be
used for Flash memory devices programmed at manufacturing time. If a Flash memory device must be
written and does not support a direct programming model, the command mechanism must be
performed in software. The CS configuration should be used in this mode. The CS signal indicates
when the address and data phases of a read or write access is occurring. The CS configuration is
controlled by configuring the CSCFG field to be 0x1and the CSCFGEXT bit to be 0 in the
EPIHBnCFG2 register.
•
Continuous read mode where address and data are separate. This sub-mode is used for real SRAMs
1248
External Peripheral Interface (EPI)
Table 17-8. Data Phase Wait State Programming
RDWSM or WRWSM Encoding in
EPIHBnTIMEn Registers
Copyright © 2012–2019, Texas Instruments Incorporated
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SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
Data Phase Wait States
1 EPI clocks
2EPI clocks
3 EPI clocks
4 EPI clocks
5 EPI clocks
6 EPI clocks
7 EPI clocks
8 EPI clocks
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