Ram Control Module Registers; M3 Ram Configuration Registers Summary; M3 Ram Error Registers Summary - Texas Instruments Concerto F28M36 Series Technical Reference Manual

RAM Control Module Registers

5.2 RAM Control Module Registers
Register Acronym Register
Description
CxDRCR1 Cx DEDRAM Config
Register 1
CxSRCR1 Cx SHRAM Config
Register 1
CxSRCR2 Cx SHRAM Config
Register 2
MSxMSEL Sx SHRAM Master
Select Register
MSxSRCR1 M3 Sx SHRAM
Config Register 1
MSxSRCR2 M3 Sx SHRAM
Config Register 2
MTOCMSGRCR M3TOC28_MSG_R
AM Config Register
CxSRCR3 Cx SHRAM Config
Register 3
CxSRCR4 Cx SHRAM Config
Register 4
CxRTESTINIT1 Cx RAM TEST and
INIT Register 1
MSxRTESTINIT1 M3 Sx RAM TEST
and INIT Register 1
MTOCRTESTINIT MTOC MSG RAM
TEST and INIT
Register
CxRINITDONE1 Cx RAM INITDONE
Register 1
MSxRINITDONE1 M3 Sx RAM
INITDONE Register
MTOCRINITDONE MTOC MSG RAM
INITDONE Register
Register Acronym
MCUNCWEADDR
MDUNCWEADDR
MCUNCREADDR
MDUNCREADDR
MCPUCREADDR
MDMACREADDR
MUEFLG
MUEFRC
472
Internal Memory
Table 5-9. M3 RAM Configuration Registers Summary
Size (x8)
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Table 5-10. M3 RAM Error Registers Summary
Size
(x8) Offset (x8) Protection
4 0x0
4 0x4
4 0x8
4 0xC
4 0x10
4 0x14
4 0x20
4 0x24
Copyright © 2012–2019, Texas Instruments Incorporated
Offset (x8) Protection
0x0 PROTECTED
0x8 PROTECTED
0xC PROTECTED
0x10 PROTECTED
+ LOCK
0x20 PROTECTED
0x24 PROTECTED
0x30 PROTECTED
0x34 PROTECTED
0x38 PROTECTED
0x40 PROTECTED
0x50 PROTECTED
0x60 PROTECTED
0x70
0x78
0x88
Reset Source Register Description
M3 M3 CPU Uncorrectable Write Error Address
Register
M3 M3 µDMA Uncorrectable Write Error Address
Register
M3 M3 CPU Uncorrectable Read Error Address
Register
M3 M3 µDMA Uncorrectable Read Error Address
Register
M3 M3 CPU Corrected Read Error Address
Register
M3 M3 µDMA Corrected Read Error Address
Register
M3 M3 Uncorrectable Error Flag Register
M3 M3 Uncorrectable Error Force Register
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
Reset
Source
M3
M3
M3
Shared
M3
M3
M3
M3
M3
M3
M3
M3
M3
M3
M3
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