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Table 15-37. Select Sources to Provide the Receive Frame-Synchronization Signal and the Effect
DLB
FSRM
1
0 or 1
1
1
15.8.16 Set the Receive Frame-Synchronization Polarity
The FSRP bit (see
active low on the FSR pin.
Table 15-38. Register Bit Used to Set Receive Frame-Synchronization Polarity
Register
Bit
PCR
2
15.8.16.1 Frame-Synchronization Pulses, Clock Signals, and Their Polarities
Receive frame-synchronization pulses can be generated internally by the sample rate generator (see
Section
15.4.2) or driven by an external source. The source of frame synchronization is selected by
programming the mode bit, FSRM, in PCR. FSR is also affected by the GSYNC bit in SRGR2. For
information about the effects of FSRM and GSYNC, see
Synchronization Mode. Similarly, receive clocks can be selected to be inputs or outputs by programming
the mode bit, CLKRM, in the PCR (see
When FSR and FSX are inputs (FSXM = FSRM= 0, external frame-synchronization pulses), the McBSP
detects them on the internal falling edge of clock, internal MCLKR, and internal CLKX, respectively. The
receive data arriving at the DR pin is also sampled on the falling edge of internal MCLKR. These internal
clock signals are either derived from an external source via CLK(R/X) pins or driven by the sample rate
generator clock (CLKG) internal to the McBSP.
When FSR and FSX are outputs, implying that they are driven by the sample rate generator, they are
generated (transition to their active state) on the rising edge of the internal clock, CLK(R/X). Similarly, data
on the DX pin is output on the rising edge of internal CLKX.
FSRP, FSXP, CLKRP, and CLKXP in the pin control register (PCR) configure the polarities of the FSR,
FSX, MCLKR, and CLKX signals, respectively. All frame-synchronization signals (internal FSR, internal
FSX) that are internal to the serial port are active high. If the serial port is configured for external frame
synchronization (FSR/FSX are inputs to McBSP), and FSRP = FSXP = 1, the external active-low frame-
synchronization signals are inverted before being sent to the receiver (internal FSR) and transmitter
(internal FSX). Similarly, if internal synchronization (FSR/FSX are output pins and GSYNC = 0) is
selected, the internal active-high frame-synchronization signals are inverted, if the polarity bit FS(R/X)P =
1, before being sent to the FS(R/X) pin.
On the transmit side, the transmit clock polarity bit, CLKXP, sets the edge used to shift and clock out
transmit data. Data is always transmitted on the rising edge of internal CLKX. If CLKXP = 1 and external
clocking is selected (CLKXM = 0 and CLKX is an input), the external falling-edge triggered input clock on
CLKX is inverted to a rising-edge triggered clock before being sent to the transmitter. If CLKXP = 1, and
internal clocking selected (CLKXM = 1 and CLKX is an output pin), the internal (rising-edge triggered)
clock, internal CLKX, is inverted before being sent out on the MCLKX pin.
SPRUHE8E – October 2012 – Revised November 2019
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on the FSR Pin (continued)
Source of Receive Frame
GSYNC
Synchronization
1
Internal FSX drives internal FSR.
0
Internal FSX drives internal FSR.
Table
15-38) determines whether frame-synchronization pulses are active high or
Name
Function
FSRP
Receive frame-synchronization polarity
FSRP = 0
FSRP = 1
Section
Copyright © 2012–2019, Texas Instruments Incorporated
FSR Pin Status
Input. If the sample rate generator is
running, external FSR is used to
synchronize CLKG and generate FSG
pulses.
Output. Receive (same as transmit)
frame synchronization is inverted as
determined by FSRP before being driven
out on the FSR pin.
Frame-synchronization pulse FSR is active high.
Frame-synchronization pulse FSR is active low.
Section
15.8.15, Set the Receive Frame-
15.8.17, Set the Receive Clock Mode).
C28 Multichannel Buffered Serial Port (McBSP)
Receiver Configuration
Reset
Type
Value
R/W
0
1127
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