Multichannel Control Registers (Mcr[1,2]); Sample Rate Generator 2 Register (Srgr2) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

McBSP Registers
Table 15-83. Sample Rate Generator 2 Register (SRGR2) Field Descriptions
Bit Field
15 GSYNC
14 Reserved
13 CLKSM
12 FSGM
11-0 FPER

15.12.8 Multichannel Control Registers (MCR[1,2])

Each McBSP has two multichannel control registers. MCR1
an R prefix) for multichannel selection operation in the receiver. MCR2
type of bits (bit with an X prefix) for the transmitter. These registers enable you to:
1170
C28 Multichannel Buffered Serial Port (McBSP)
Value Description
Clock synchronization mode bit for CLKG. GSYNC is used only when the input clock source
for the sample rate generator is external—on the MCLKR pin.
When GSYNC = 1, the clock signal (CLKG) and the frame-synchronization signal (FSG)
generated by the sample rate generator are made dependent on pulses on the FSR pin.
0 No clock synchronization
CLKG oscillates without adjustment, and FSG pulses every (FPER + 1) CLKG cycles.
1 Clock synchronization
• CLKG is adjusted as necessary so that it is synchronized with the input clock on the
MCLKR pin.
• FSG pulses. FSG only pulses in response to a pulse on the FSR pin.
The frame-synchronization period defined in FPER is ignored.
For more details, see
External Clock.
Reserved
0 Sample rate generator input clock mode bit. The sample rate generator can accept an input
clock signal and divide it down according to CLKGDV to produce an output clock signal,
CLKG. The frequency of CLKG is:)
CLKG frequency = (input clock frequency)/ (CLKGDV + 1
CLKSM is used in conjunction with the SCLKME bit to determine the source for the input
clock.
A reset selects the CPU clock as the input clock and forces the CLKG frequency to ½ the
LSPCLK frequency.
The input clock for the sample rate generator is taken from the MCLKR pin, depending on
the value of the SCLKME bit of PCR:
SCLKME
0
1
1 The input clock for the sample rate generator is taken from the LSPCLK or from the MCLKX
pin, depending on the value of the SCLKME bit of PCR:
SCLKME
0
1
Sample rate generator transmit frame-synchronization mode bit. The transmitter can get
frame synchronization from the FSX pin (FSXM = 0) or from inside the McBSP (FSXM = 1).
When FSXM = 1, the FSGM bit determines how the McBSP supplies frame-synchronization
pulses.
0 If FSXM = 1, the McBSP generates a transmit frame-synchronization pulse when the content
of DXR[1,2] is copied to XSR[1,2].
1 If FSXM = 1, the transmitter uses frame-synchronization pulses generated by the sample
rate generator. Program the FWID bits to set the width of each pulse. Program the FPER bits
to set the period between pulses.
0-FFFh Frame-synchronization period bits for FSG. The sample rate generator can produce a clock
signal, CLKG, and a frame-synchronization signal, FSG. The period between frame-
synchronization pulses on FSG is (FPER + 1) CLKG cycles. The 12 bits of FPER allow a
frame-synchronization period of 1 to 4096 CLKG cycles:
0 ≤ FPER ≤ 4095
1 ≤ (FPER + 1) ≤ 4096 CLKG cycles
The width of each frame-synchronization pulse on FSG is defined by the FWID bits.
Copyright © 2012–2019, Texas Instruments Incorporated
Section 15.4.3, Synchronizing Sample Rate Generator Outputs to an
CLKSM
0
0
CLKSM
1
1
(Table 15-84) has control and status bits (with
(Table
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
Input Clock For
Sample Rate Generator
Reserved
Signal on MCLKR pin
Input Clock For
Sample Rate Generator
LSPCLK
Signal on MCLKX pin
15-85) contains the same
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