Set The Receive Data Delay; Companding Processes For Reception And For Transmission; Register Bits Used To Set The Receive Data Delay - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Receiver Configuration
15.8.11.1 Companding
Companding (COMpressing and exPANDing) hardware allows compression and expansion of data in
either μ-law or A-law format. The companding standard employed in the United States and Japan is μ-law.
The European companding standard is referred to as A-law. The specifications for μ-law and A-law log
PCM are part of the CCITT G.711 recommendation.
A-law and μ-law allow 13 bits and 14 bits of dynamic range, respectively. Any values outside this range
are set to the most positive or most negative value. Thus, for companding to work best, the data
transferred to and from the McBSP via the CPU or DMA controller must be at least 16 bits wide.
The μ-law and A-law formats both encode data into 8-bit code words. Companded data is always 8 bits
wide; the appropriate word length bits (RWDLEN1, RWDLEN2, XWDLEN1, XWDLEN2) must therefore be
set to 0, indicating an 8-bit wide serial data stream. If companding is enabled and either of the frame
phases does not have an 8-bit word length, companding continues as if the word length is 8 bits.
Figure 15-45 illustrates the companding processes. When companding is chosen for the transmitter,
compression occurs during the process of copying data from DXR1 to XSR1. The transmit data is
encoded according to the specified companding law (A-law or μ-law). When companding is chosen for the
receiver, expansion occurs during the process of copying data from RBR1 to DRR1. The receive data is
decoded to 2's-complement format.
Figure 15-45. Companding Processes for Reception and for Transmission
RSR1
DR
DX
15.8.11.2 Format of Expanded Data
For reception, the 8-bit compressed data in RBR1 is expanded to left-justified 16-bit data in DRR1. The
RJUST bit of SPCR1 is ignored when companding is used.
15.8.11.3 Companding Internal Data
If the McBSP is otherwise unused (the serial port transmit and receive sections are reset), the
companding hardware can compand internal data. See
Data.
15.8.11.4 Option to Receive LSB First
Normally, the McBSP transmits or receives all data with the most significant bit (MSB) first. However,
certain 8-bit data protocols (that do not use companded data) require the least significant bit (LSB) to be
transferred first. If you set RCOMPAND = 01b in RCR2, the bit ordering of 8-bit words is reversed during
reception. Similar to companding, this feature is enabled only if the appropriate word length bits are set to
0, indicating that 8-bit words are to be transferred serially. If either phase of the frame does not have an 8-
bit word length, the McBSP assumes the word length is eight bits and LSB-first ordering is done.

15.8.12 Set the Receive Data Delay

The RDATDLY bits (see
Register Bit
RCR2 1-0
1122
C28 Multichannel Buffered Serial Port (McBSP)
8
RBR1
Expand
8
Compress
XSR1
Table 15-31) determine the length of the data delay for the receive frame.
Table 15-31. Register Bits Used to Set the Receive Data Delay
Name Function
RDATDLY Receive data delay
RDATDLY = 00
RDATDLY = 01
RDATDLY = 10
Copyright © 2012–2019, Texas Instruments Incorporated
16
DRR1
To CPU or DMA controller
16
DXR1
From CPU or DMA controller
Section 15.1.5.2, Capability to Compand Internal
0-bit data delay
1-bit data delay
2-bit data delay
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
Reset
Type Value
R/W 00
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