Epi Main Baud Rate (Epibaud2) Register, Offset 0X008; Epi Main Baud Rate (Epibaud2) Register [Offset 0X008]; Epi Main Baud Rate (Epibaud2) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Table of Contents

17.11.3 EPI Main Baud Rate (EPIBAUD2) Register, offset 0x008

The system clock is used internally to the EPI Controller. The baud rate counter can be used to divide the

system clock down to control the speed on the external interface. If the mode selected emits an external

EPI clock, this register defines the EPI clock emitted. If the mode selected does not use an EPI clock, this

properly so that the speed of the external bus corresponds to the speed of the external peripheral and

puts acceptable current load on the pins. COUNT0 and COUNT1 are used in quad chip select mode when

different baud rates are selected, See

used, COUNT0 is associated with the address range specified by CS2 and COUNT1 is associated with

the address range specified by CS3.

The COUNTn field is not a straight divider or count. The EPI Clock on EPI0S31 is related to the COUNTn

field and the system clock as follows:

If COUNTn = 0,

EPIClockFreq = SystemClockFreq

EPIClockFreq = SystemClockFreq / ([Countn / 2] + 1) × 2

where the symbol around COUNTn/2 is the floor operator; meaning the largest integer less than or equal

to COUNTn/2.

So, for example, a COUNTn of 0x0001 results in a clock rate of 1/2 (system clock); a COUNTn of 0x0002

or 0x0003 results in a clock rate of 1/4 (system clock)

Figure 17-30. EPI Main Baud Rate (EPIBAUD2) Register [offset 0x008]

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 17-16. EPI Main Baud Rate (EPIBAUD2) Register Field Descriptions

SPRUHE8E – October 2012 – Revised November 2019

Submit Documentation Feedback

Section 17.11.8

CS3 Baud Rate Counter 1

This bit field contains a counter used to divide the system clock by the count.

A count of 0 means the system clock is used as is.

This bit field is only valid when quad chip selects are enabled by setting the CSCFGEXT bit to 1

and the CSCFG field to 0x1 or 0x2. In addition, the CSBAUD bit must be set in the EPIHBnCFG2

CS2 Baud Rate Counter 0

This bit field contains a counter used to divide the system clock by the count.

A count of 0 means the system clock is used as is.

This bit field is only valid when quad chip selects are enabled by setting the CSCFGEXT to 1 and

the CSCFG field to 0x1 or 0x2. In addition, the CSBAUD bit must be set in the EPIHBnCFG2

17.11.9. If different baud rates are

External Peripheral Interface (EPI)

Table of Contents