Dma Channel Map Assignment (Dmachmap3) Register, Offset 0X51C; Dma Channel Map Assignment (Dmachmap2) Register; Dma Channel Map Assignment (Dmachmap2) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

µDMA Register Descriptions
Figure 16-30. DMA Channel Map Assignment (DMACHMAP2) Register
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16-37. DMA Channel Map Assignment (DMACHMAP2) Register Field Descriptions
Bit Field
31-28
27-24
23-20
19-16
15-12
11-8
7-4
3-0

16.7.22 DMA Channel Map Assignment (DMACHMAP3) Register, offset 0x51C

Each bit of the DMACHMAP0 register controls the channel assignments for the first, second, and third
mapping.
1222
M3 Micro Direct Memory Access ( µDMA)
Value Description
0 Channel 23 First Assignment
1 Channel 23 Second Assignment
2 Channel 23 Third Assignment
3 Reserved
0 Channel 22 First Assignment
1 Channel 22 Second Assignment
2 Channel 22 Third Assignment
3 Reserved
0 Channel 21 First Assignment
1 Channel 21 Second Assignment
2 Channel 21 Third Assignment
3 Reserved
0 Channel 20 First Assignment
1 Channel 20 Second Assignment
2 Channel 20 Third Assignment
3 Reserved
0 Channel 19 First Assignment
1 Channel 19 Second Assignment
2 Channel 19 Third Assignment
3 Reserved
0 Channel 18 First Assignment
1 Channel 18 Second Assignment
2 Channel 18 Third Assignment
3 Reserved
0 Channel 17 First Assignment
1 Channel 17 Second Assignment
2 Channel 17 Third Assignment
3 Reserved
0 Channel 16 First Assignment
1 Channel 16 Second Assignment
2 Channel 16 Third Assignment
3 Reserved
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CHMAP2
R/W
SPRUHE8E – October 2012 – Revised November 2019
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