Adc Interrupt Trigger Soc Select 1 Register (Adcintsocsel1) (Address Offset 14H); Adc Interrupt Trigger Soc Select 1 Register (Adcintsocsel1) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Table 10-14. ADC Sample Mode Register (ADCSAMPLEMODE) Field Descriptions (continued)
Bit Field
3 SIMULEN6
2 SIMULEN4
1 SIMULEN2
0 SIMULEN0
NOTE: The following ADC Interrupt SOC Select Registers are EALLOW protected.
Figure 10-30. ADC Interrupt Trigger SOC Select 1 Register (ADCINTSOCSEL1) (Address Offset 14h)
15 14 13 12
SOC7 SOC6
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-15. ADC Interrupt Trigger SOC Select 1 Register (ADCINTSOCSEL1) Register Field
Bit Field
15--0 SOCx
(x = 7 to 0)
SPRUHE8E – October 2012 – Revised November 2019
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Value Description
Simultaneous sampling enable for SOC6/SOC7. Couples SOC6 and SOC7 in simultaneous
sampling mode. See Section 10.3.6
converting SOC6 or SOC7.
0 Single sample mode set for SOC6 and SOC7. All bits of CHSEL field define channel to be
converted. EOC6 associated with SOC6. EOC7 associated with SOC7. SOC6's result placed in
ADCRESULT6 register. SOC7's result placed in ADCRESULT7.
1 Simultaneous sample for SOC6 and SOC7. Lowest three bits of CHSEL field define the pair of
channels to be converted. EOC6 and EOC7 associated with SOC6 and SOC7 pair. SOC6's and
SOC7's results will be placed in ADCRESULT6 and ADCRESULT7 registers, respectively.
Simultaneous sampling enable for SOC4/SOC5. Couples SOC4 and SOC5 in simultaneous
sampling mode. See Section 10.3.6
converting SOC4 or SOC5.
0 Single sample mode set for SOC4 and SOC5. All bits of CHSEL field define channel to be
converted. EOC4 associated with SOC4. EOC5 associated with SOC5. SOC4's result placed in
ADCRESULT4 register. SOC5's result placed in ADCRESULT5.
1 Simultaneous sample for SOC4 and SOC5. Lowest three bits of CHSEL field define the pair of
channels to be converted. EOC4 and EOC5 associated with SOC4 and SOC5 pair. SOC4's and
SOC5's results will be placed in ADCRESULT4 and ADCRESULT5 registers, respectively.
Simultaneous sampling enable for SOC2/SOC3. Couples SOC2 and SOC3 in simultaneous
sampling mode. See Section 10.3.6
converting SOC2 or SOC3.
0 Single sample mode set for SOC2 and SOC3. All bits of CHSEL field define channel to be
converted. EOC2 associated with SOC2. EOC3 associated with SOC3. SOC2's result placed in
ADCRESULT2 register. SOC3's result placed in ADCRESULT3.
1 Simultaneous sample for SOC2 and SOC3. Lowest three bits of CHSEL field define the pair of
channels to be converted. EOC2 and EOC3 associated with SOC2 and SOC3 pair. SOC2's and
SOC3's results will be placed in ADCRESULT2 and ADCRESULT3 registers, respectively.
Simultaneous sampling enable for SOC0/SOC1. Couples SOC0 and SOC1 in simultaneous
sampling mode. See Section 10.3.6
converting SOC0 or SOC1.
0 Single sample mode set for SOC0 and SOC1. All bits of CHSEL field define channel to be
converted. EOC0 associated with SOC0. EOC1 associated with SOC1. SOC0's result placed in
ADCRESULT0 register. SOC1's result placed in ADCRESULT1.
1 Simultaneous sample for SOC0 and SOC1. Lowest three bits of CHSEL field define the pair of
channels to be converted. EOC0 and EOC1 associated with SOC0 and SOC1 pair. SOC0's and
SOC1's results will be placed in ADCRESULT0 and ADCRESULT1 registers, respectively.
11 10 9
SOC5 SOC4
R/W-0 R/W-0
Value Description
SOCx ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOCx. This field
overrides the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOCx. TRIGSEL field determines SOCx trigger.
01 ADCINT1 will trigger SOCx. TRIGSEL field is ignored.
10 ADCINT2 will trigger SOCx. TRIGSEL field is ignored.
11 Invalid selection.
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for details. This bit should not be set when the ADC is actively
for details. This bit should not be set when the ADC is actively
for details. This bit should not be set when the ADC is actively
for details. This bit should not be set when the ADC is actively
8 7 6 5
SOC3 SOC2
R/W-0 R/W-0
Descriptions
Analog-to-Digital Converter (ADC)
4 3 2 1
SOC1 SOC0
R/W-0 R/W-0
Analog Subsystem
0
919