Ethernet Mac Receive Control (Macrctl) Register; Ethernet Mac Interrupt Mask (Macim) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Table 19-4. Ethernet MAC Interrupt Mask (MACIM) Register Field Descriptions
Bit Field
31-7 Reserved
6 PHYINT
5 MDINTM
4 RXERM
3 FOVM
2 TXEMPM
1 TXERM
0 RXINTM
19.6.3 Ethernet MAC Receive Control (MACRCTL) Register, offset 0x008
The Ethernet MAC Receive Control (MACRCTL) register is shown and described in the figure and table
below.
31
15
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
SPRUHE8E – October 2012 – Revised November 2019
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Value Description
Reserved
Mask PHY Interrupt
0 The PHYINT interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the PHYINT bit in the MACRIS/MACIACK
register is set.
Mask MII Transaction Complete
0 The MDINT interrupt is suppressed and not sent to the interrupt controller
1 An interrupt is sent to the interrupt controller when the MDINT bit in the MACRIS/MACIACK register
is set.
Mask Receive Error
0 The RXER interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the RXER bit in the MACRIS/MACIACK register
is set
Mask FIFO Overrun
0 The FOV interrupt is suppressed and not sent to the interrupt controller
1 An interrupt is sent to the interrupt controller when the FOV bit in the MACRIS/MACIACK register is
set.
Mask Transmit FIFO Empty
0 The TXEMP interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the TXEMP bit in the MACRIS/MACIACK
register is set.
Mask Transmit Error
0 The TXER interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the TXER bit in the MACRIS/MACIACK register
is set.
Mask Packet Received
0 The RXINT interrupt is suppressed and not sent to the interrupt controller.
1 An interrupt is sent to the interrupt controller when the RXINT bit in the MACRIS/MACIACK register
is set.
Figure 19-6. Ethernet MAC Receive Control (MACRCTL) Register
R-0
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
5 4 3
RSTFIFO BADCRC
R/W-0 R/W-1
M3 Ethernet Media Access Controller (EMAC)
Ethernet MAC Register Descriptions
2 1
PRMS AMUL
R-0 R/W-0
16
0
RXEN
R/W-0
1427