If1 Mask Register (Can If1Msk) [Offset = 0X104] - Texas Instruments Concerto F28M36 Series Technical Reference Manual

CAN Control Registers
Table 23-18. IF1 and IF2 Command Register Field Descriptions (continued)
Bit Field
16 Data B
15 Busy
14 DMAactive
13-8 Reserved
7-0 Message Number
23.15.15 IF1 and IF2 Mask Registers (CAN IF1MSK, CAN IF2MSK)
The bits of the IF1 and IF2 Mask registers mirror the mask bits of a message object. The function of the
relevant message objects bits is described in
NOTE: While the Busy bit of the IF1 or IF2 Command Register is one, the IF1 or IF2 Register Set is
write protected.
31 30 29 28
MXtd MDir Rsvd
R/WP- R/WP- R-1
1 1
15
LEGEND: R = Read; WP = Protected Write (protected by Busy bit); -n = value after reset
1594
M3 Controller Area Network (CAN)
Value Description
Access Data Bytes 4-7
0 Data Bytes 4-7 will not be changed.
1 Direction = Read: The Data Bytes 4-7 will be transferred from the message object addressed
by Message Number (Bits [7:0]) to the corresponding IF1 or IF2 register set.
Direction = Write: The Data Bytes 4-7 will be transferred from the IF1 or F2 register set to the
message object addressed by Message Number (Bits [7:0]).
Note: The duration of the message transfer is independent of the number of bytes to be
transferred.
Busy Flag
0 No transfer between IF1 or IF2 register Set and Message RAM is in progress.
1 Transfer between IF1 or IF2 register Set and Message RAM is in progress.
This bit is set to one after the message number has been written to bits [7:0]. IF1 or IF2
register set will be write protected. The bit is cleared after read/write action has been finished.
Activation of DMA feature for subsequent internal IF1 and IF2 update
0 DMA request line is independent of IF1 or IF2 activities.
1 DMA is requested after completed transfer between IF1 or IF2 register set and Message RAM.
The DMA request remains active until the first read or write to one of the IF1 or IF2 registers;
an exception is a write to Message Number (Bits [7:0]) when DMAactive is one.
Note: Due to the auto reset feature of the DMAactive bit, this bit has to be set for each
subsequent DMA cycle separately.
Reserved
Number of message object in Message RAM which is used for data transfer
0x00 Invalid message number
0x01-0x20 Valid message numbers
0x21-0xFF Invalid message numbers
Figure 23-34. IF1 Mask Register (CAN IF1MSK) [offset = 0x104]
Copyright © 2012–2019, Texas Instruments Incorporated
Section 23.14.1.
Msk[28:16]
R/WP-0x1FFF
Msk[15:0]
R/WP-0xFFFF
SPRUHE8E – October 2012 – Revised November 2019
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