Ecc Status Register (Fecc_Status); Test Data Out Low Register (Fecc_Foutl_Test) Field Descriptions; Ecc Status Register (Fecc_Status) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Table 5-146. Test Data Out Low Register (FECC_FOUTL_TEST) Field Descriptions

5.4.4.18 ECC Status Register (FECC_STATUS)

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-147. ECC Status Register (FECC_STATUS) Field Descriptions

SPRUHE8E – October 2012 – Revised November 2019

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Low double word test data out. Holds bits 31:0 of the data out of the selected ECC block.

Figure 5-139. ECC Status Register (FECC_STATUS)

Test mode ECC single bit error indicator. When 1, indicates that the single bit error is in

check bits. When 0, indicates that the single bit error is in data bits (if SINGLE_ERR

field is also set).

Test mode data bit error position. Holds the bit position in the 64 bit data where the

error occurred.Test mode single bit error position. Holds the bit position where the

single bit error occurred. The position is interpreted depending on whether the

CHK_ERR bit indicates a check bit or a data bit. If CHK_ERR indicates a check bit

error, the error position could range from 0 to 7 or it could range from 0 to 63.

Test mode ECC double bit error. When 1 indicates that the ECC test resulted in an

uncorrectable bit error.

Test mode ECC single bit error. When 1 indicates that the ECC test resulted in a single

Flash Registers

Internal Memory

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